公开(公告)号：US10901742B2

公开(公告)日：2021-01-26

申请号：US16364570

申请日：2019-03-26

Applicant: Arm Limited

Inventor： Yasuo Ishii ,  Muhammad Umar Farooq

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus and method are provided for making predictions for instruction flow changing instructions. The apparatus has a fetch queue that identifies a sequence of instructions to be fetched for execution by execution circuitry, and prediction circuitry for making predictions in respect of instruction flow changing instructions, and for controlling which instructions are identified in the fetch queue in dependence on the predictions. The prediction circuitry is arranged, during each prediction iteration, to make a prediction for a predict block comprising a sequence of M instruction addresses, in order to identify whether that predict block contains the instruction address for an instruction flow changing instruction that is predicted as taken. During each prediction iteration, the prediction circuitry is arranged by default to access a prediction storage in order to produce prediction information for instructions associated with a specified block of instruction addresses (including at least the predict block being considered), and to use that prediction information to make the prediction for the predict block. Buffer storage is used to retain the prediction information obtained from the prediction storage during one or more previous prediction iterations, and detection circuitry is used to detect when a current predict block being considered during a current prediction iteration comprises one or more instruction addresses for which the associated prediction information is retained in the buffer storage. In that event, the above default behaviour is not adopted, and an override condition is triggered to cause the prediction information for those one or more instruction addresses to be obtained from the buffer storage rather than from the prediction storage, giving rise to a power saving.

公开(公告)号：US11526359B2

公开(公告)日：2022-12-13

申请号：US16150372

申请日：2018-10-03

Applicant: Arm Limited

Inventor： Yasuo Ishii ,  Muhammad Umar Farooq ,  Chris Abernathy

IPC: G06F9/38 ,  G06F9/30

Abstract: A data processing apparatus is provided that includes global-history prediction circuitry that provides a prediction of an outcome of a given control flow instruction based on a result of execution of one or more previous control flow instructions. Correction circuitry provides a corrected prediction of the global-history prediction circuitry in respect of the given control flow instruction and cache circuitry, separate from the correction circuitry, stores the corrected prediction in respect of the given control flow instruction.

公开(公告)号：US11507372B2

公开(公告)日：2022-11-22

申请号：US17064983

申请日：2020-10-07

Applicant: Arm Limited

Inventor： Michael Brian Schinzler ,  Yasuo Ishii ,  Muhammad Umar Farooq ,  Jason Lee Setter

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875

Abstract: An apparatus and method are provided for processing instructions fetched from memory. Decode circuitry is used to decode the fetched instructions in order to produce decoded instructions, and downstream circuitry then processes the decoded instructions in order to perform the operations specified by those decoded instructions. Dispatch circuitry is arranged to dispatch to the downstream circuitry up to N decoded instructions per dispatch cycle, and is arranged to determine, based on a given candidate sequence of decoded instructions being considered for dispatch in a given dispatch cycle, whether at least one resource conflict within the downstream circuitry would occur in the event that the given candidate sequence of decoded instructions is dispatched in the given dispatch cycle. The dispatch circuitry has resource checking circuitry arranged, by default, to perform a resource checking operation during the given dispatch cycle to generate, for the given candidate sequence of decoded instructions, resource conflict information used to determine whether a resource conflict would occur. Resource conflict information cache storage is provided to maintain, for one or more sequences of decoded instructions, associated resource conflict information. In the event that the given candidate sequence matches one of the sequences for which associated resource conflict information is cached, the dispatch circuitry employs the associated cached resource conflict information to determine whether a resource conflict would occur, instead of invoking the resource checking circuitry to perform the resource checking operation.

公开(公告)号：US11455253B2

公开(公告)日：2022-09-27

申请号：US17060624

申请日：2020-10-01

Applicant: Arm Limited

Inventor： Yasuo Ishii ,  James David Dundas ,  Chang Joo Lee ,  Muhammad Umar Farooq

IPC: G06F12/0864 ,  G06F12/121 ,  G06F12/0873 ,  G06F12/0811

Abstract: An apparatus comprises first-level and second-level set-associative caches each comprising the same number of sets of cache entries. Indexing circuitry generates, based on a lookup address, a set index identifying which set of the first-level set-associative cache or the second-level set-associative cache is a selected set of cache entries to be looked up for information associated with the lookup address. The indexing circuitry generates the set index using an indexing scheme which maps the lookup address to the same set index for both the first-level set-associative cache and the second-level set-associative cache. This can make migration of cached information between the cache levels more efficient, which can be particularly useful for caches with high access frequency, such as branch target buffers for a branch predictor.

公开(公告)号：US11029959B2

公开(公告)日：2021-06-08

申请号：US16120674

申请日：2018-09-04

Applicant: Arm Limited

Inventor： Yasuo Ishii ,  Muhammad Umar Farooq ,  Chris Abernathy

IPC: G06F9/38

Abstract: Branch prediction circuitry processes blocks of instructions and provides instruction fetch circuitry with indications of predicted next blocks of instructions to be retrieved from memory. Main branch target storage stores branch target predictions for branch instructions in the blocks of instructions. Secondary branch target storage caches the branch target predictions from the main branch target storage. Look-ups in the secondary branch target storage and the main branch target storage are performed in parallel. The main branch target storage is set-associative and an entry in the main branch target storage comprises multiple ways, wherein each way of the multiple ways stores a branch target prediction for one branch instruction. The branch prediction circuitry stores a way prediction for which of the multiple ways contain the branch target predictions for a predicted next block of instructions and stores a flag associated with the way prediction indicating whether all branch target predictions stored for the predicted next block of instructions in the main branch target storage are also stored in the secondary branch target storage. An active value of the flag suppresses the look-up in the main branch target storage for the predicted next block of instructions.

公开(公告)号：US11086629B2

公开(公告)日：2021-08-10

申请号：US16185073

申请日：2018-11-09

Applicant: Arm Limited

Inventor： Yasuo Ishii ,  Muhammad Umar Farooq ,  Chris Abernathy

IPC: G06F9/38 ,  G06F9/30

Abstract: Apparatus and a method of operating the same is disclosed. Instruction fetch circuitry is provided to fetch a block of instructions from memory and branch prediction circuitry to generate branch prediction indications for each branch instruction present in the block of instructions. The branch prediction circuitry is responsive to identification of a first conditional branch instruction in the block of instructions that is predicted to be taken to modify a branch prediction indication generated for the first conditional branch instruction to include a subsequent branch status indicator. When there is a subsequent branch instruction after the first conditional branch instruction in the block of instructions that is predicted to be taken the subsequent branch status indicator has a first value, and otherwise the subsequent branch status indicator has a second value. This supports improved handling of a misprediction as taken.

公开(公告)号：US10990403B1

公开(公告)日：2021-04-27

申请号：US16752995

申请日：2020-01-27

Applicant: Arm Limited

Inventor： Joseph Michael Pusdesris ,  Yasuo Ishii ,  Muhammad Umar Farooq

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/48

Abstract: An apparatus is described, comprising processing circuitry to speculatively execute an earlier instruction and a later instruction by generating a prediction of an outcome of the earlier instruction and a prediction of an outcome of the later instruction, wherein the prediction of the outcome of the earlier instruction causes a first control flow path to be executed. The apparatus also comprises storage circuitry to store the outcome of the later instruction in response to the later instruction completing, and flush circuitry to generate a flush in response to the prediction of the outcome of the earlier instruction being incorrect. When re-executing the later instruction in a second control flow path following the flush, the processing circuitry is adapted to generate the prediction of the outcome of the later instruction as the outcome stored in the storage circuitry during execution of the first control flow path.

公开(公告)号：US10176104B2

公开(公告)日：2019-01-08

申请号：US15281226

申请日：2016-09-30

Applicant: ARM LIMITED

Inventor： Vasu Kudaravalli ,  Matthew Paul Elwood ,  Adam George ,  Muhammad Umar Farooq ,  Michael Filippo

IPC: G06F9/40 ,  G06F9/45 ,  G06F12/02 ,  G06F12/0875 ,  G06F9/38 ,  G06F9/30 ,  G06F8/41

Abstract: An apparatus comprises processing circuitry, an instruction cache, decoding circuitry to decode program instructions fetched from the cache to generate macro-operations to be processed by the processing circuitry, and predecoding circuitry to perform a predecoding operation on a block of program instructions fetched from a data store to generate predecode information to be stored to the cache with the block of instructions. In one example the predecoding operation comprises generating information on how many macro-operations are to generated by the decoding circuitry for a group of one or more program instructions. In another example the predecoding operation comprises generating information indicating whether at least one of a given subset of program instructions within the prefetched block is a branch instruction.

公开(公告)号：US12045620B2

公开(公告)日：2024-07-23

申请号：US17554573

申请日：2021-12-17

Applicant: Arm Limited

Inventor： Yasuo Ishii ,  Muhammad Umar Farooq ,  William Elton Burky ,  Michael Brian Schinzler ,  Jason Lee Setter ,  David Gum Lim

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/384 ,  G06F9/3867

Abstract: A data processing apparatus is provided that comprises rename circuitry for performing a register rename stage of a pipeline in respect of a stream of operations. Move elimination circuitry performs a move elimination operation on the stream of operations in which a move operation is eliminated and the register rename stage performs an adjustment of an identity of registers in the stream of operations to compensate for the move operation being eliminated and demotion circuitry reverses or inhibits the adjustment in response to one or more conditions being met.

公开(公告)号：US11379239B2

公开(公告)日：2022-07-05

申请号：US16364557

申请日：2019-03-26

Applicant: Arm Limited

Inventor： Yasuo Ishii ,  Muhammad Umar Farooq

IPC: G06F15/00 ,  G06F9/30 ,  G06F9/38 ,  G06F9/32

Abstract: An apparatus and method are provided for making predictions for instruction flow changing instructions. The apparatus has a fetch queue that identifies a sequence of instructions to be fetched for execution by execution circuitry, and prediction circuitry for making predictions in respect of instruction flow changing instructions, and for controlling which instructions are identified in the fetch queue in dependence on the predictions. The prediction circuitry has a target prediction storage used to identify target addresses for instruction flow changing instructions that are predicted as taken. The target prediction storage comprises at least one entry that is configurable as a multi-taken entry to indicate that a source instruction flow changing instruction identified by that entry is a first instruction flow changing instruction with an associated first target address that identifies a series of instructions that is expected to exhibit static behaviour and that terminates with a second instruction flow changing instruction, where the second instruction flow changing instruction is unconditionally taken and has an associated second target address. The prediction circuitry is arranged, when making a prediction for a chosen instruction flow changing instruction that is identified by a multi-taken entry in the target prediction storage, to identify with reference to target address information stored in that multi-taken entry both the series of instructions and a target instruction at the second target address. It then causes the series of instructions and the target instruction to be identified in the fetch queue, and begins making further predictions starting from the target instruction at the second target address.