公开(公告)号：US10248572B2

公开(公告)日：2019-04-02

申请号：US15271611

申请日：2016-09-21

Applicant: ARM Limited

Inventor： Jose Gonzalez Gonzalez ,  Alex James Waugh ,  Adnan Khan

IPC: G06F12/0895 ,  G06F12/1045 ,  G06F12/0831

Abstract: An apparatus and method are provided for operating a virtually indexed, physically tagged cache. The apparatus has processing circuitry for performing data processing operations on data, and a virtually indexed, physically tagged cache for storing data for access by the processing circuitry. The cache is accessed using a virtual address portion of a virtual address in order to identify a number of cache entries, and then physical address portions stored in those cache entries are compared with the physical address derived from the virtual address in order to detect whether a hit condition exists. Further, snoop request processing circuitry is provided that is responsive to a snoop request specifying a physical address, to determine a plurality of possible virtual address portions for the physical address, and to perform a snoop processing operation in order to determine whether the hit condition is detected for a cache entry when accessing the cache storage using the plurality of possible virtual address portions. On detection of the hit condition a coherency action is performed in respect of the cache entry causing the hit condition. This allows effective detection and removal of aliasing conditions that can arise when different virtual addresses associated with the same physical address cause cache entries in different sets of the cache to be accessed.

公开(公告)号：US09652385B1

公开(公告)日：2017-05-16

申请号：US14953093

申请日：2015-11-27

Applicant: ARM Limited

Inventor： Gregory Andrew Chadwick ,  Adnan Khan

IPC: G06F12/08 ,  G06F9/52 ,  G06F9/38 ,  G06F12/0802 ,  G06F12/0815

CPC classification number: G06F9/528 ,  G06F9/3834 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/1054 ,  G06F2212/1024 ,  G06F2212/1032

Abstract: An apparatus and method are provided for handling atomic update operations. The apparatus has a cache storage to store data for access by processing circuitry, the cache storage having a plurality of cache lines. Atomic update handling circuitry is used to handle performance of an atomic update operation in respect of data at a specified address. When data at the specified address is determined to be stored within a cache line of the cache storage, the atomic update handling circuitry performs the atomic update operation on the data from that cache line. Hazard detection circuitry is used to trigger deferral of performance of the atomic update operation upon detecting that a linefill operation for the cache storage is pending that will cause a chosen cache line to be populated with data that includes data at the specified address. The linefill operation causes the apparatus to receive a sequence of data portions that collectively form the data for storing in the chosen cache line. Partial linefill notification circuitry is used to provide partial linefill information to the atomic update handling circuitry during the linefill operation, and the atomic update handling circuitry is arranged to initiate the atomic update operation responsive to detecting from the partial linefill information that the data at the specified address is available for the chosen cache line. This can provide a performance benefit, by avoiding the need for the atomic update handling circuitry to await completion of the linefill operation before beginning the atomic update operation.

公开(公告)号：US11334486B2

公开(公告)日：2022-05-17

申请号：US16305165

申请日：2017-04-27

Applicant: ARM LIMITED

Inventor： Adnan Khan ,  Alex James Waugh ,  Jose Gonzalez-Gonzalez

IPC: G06F12/08 ,  G06F12/084 ,  G06F12/0817 ,  G06F12/0831

Abstract: An apparatus (300) for processing data comprises a plurality of memory access request sources (102,104) which generate memory access requests. Each of the memory access request sources has a local memory (106,108), and the apparatus also includes a shared memory (110). When the memory access requests are atomic memory access requests, contention may arise over common data. When this occurs, the present technique triggers a switch of processing data in the local memory of a memory access request source to processing data in the shared memory.