公开(公告)号：US12124455B2

公开(公告)日：2024-10-22

申请号：US18331833

申请日：2023-06-08

申请人： OPEN TEXT CORPORATION

发明人： Shu-Shang Sam Wei ,  Shuaib Hasan Khwaja ,  Pankaj Pradhan

IPC分类号： G06F15/16 ,  G06F9/38 ,  G06F12/02 ,  G06F16/22 ,  G06F16/2455 ,  G06F16/28 ,  H04L67/1097 ,  H04L67/568 ,  H04L67/2885

CPC分类号： G06F16/24553 ,  G06F9/3834 ,  G06F12/0261 ,  G06F16/22 ,  G06F16/24552 ,  G06F16/24562 ,  G06F16/284 ,  H04L67/1097 ,  H04L67/568 ,  H04L67/2885

摘要： Systems and methods for managing concurrent access to a shared resource in a distributed computing environment are provided. A reference counter counts is incremented for every use of an object subtype in a session and decremented for every release of an object subtype in a session. A session counter is incremented upon the first instance of fetching an object type into a session cache and decremented upon having no instances of the object type in use in the session. When both the reference counter and the session counter are zero, the object type may be removed from the cache.

公开(公告)号：US20240320010A1

公开(公告)日：2024-09-26

申请号：US18732604

申请日：2024-06-03

申请人： Samsung Electronics Co., Ltd.

发明人： Chao YANG ,  Wentao WU ,  Glenn YU ,  Wei ZHAO ,  FNU VIKRAM SINGH ,  Xiaoyi ZHANG ,  Yong YANG

IPC分类号： G06F9/38 ,  G06F3/06 ,  G06F9/30 ,  G06F9/54 ,  G06F11/30

CPC分类号： G06F9/3856 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/30018 ,  G06F9/3834 ,  G06F9/544 ,  G06F11/3051

摘要： A method may include determining, with a queue availability module, that an entry is available in a queue, asserting a bit in a register based on determining that an entry is available in the queue, determining, with a processor, that the bit is asserted, and processing, with the processor, the entry in the queue based on determining that the bit is asserted. The method may further include storing the register in a tightly coupled memory associated with the processor. The method may further include storing the queue in the tightly coupled memory. The method may further include determining, with the queue availability module, that an entry is available in a second queue, and asserting a second bit in the register based on determining that an entry is available in the second queue. The method may further include finding the first bit in the register using a find first instruction.

公开(公告)号：US20240248844A1

公开(公告)日：2024-07-25

申请号：US18587289

申请日：2024-02-26

申请人： Apple Inc.

发明人： Francesco Spadini ,  Gideon Levinsky ,  Mridul Agarwal

IPC分类号： G06F12/0804 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F12/0804 ,  G06F9/30043 ,  G06F9/3826 ,  G06F9/3834 ,  G06F2212/601

摘要： In an embodiment, a processor implements a different atomicity size (for memory consistency order) than the operation size. More particularly, the processor may implement a smaller atomicity size than the operation size. For example, for multiple register loads, the atomicity size may be the register size. In another example, the vector element size may be the atomicity size for vector load instructions. In yet another example, multiple contiguous vector elements, but fewer than all the vector elements in a vector register, may be the atomicity size for vector load instructions.

公开(公告)号：US20240211441A1

公开(公告)日：2024-06-27

申请号：US18594969

申请日：2024-03-04

申请人： Fisher Controls International LLC

发明人： Mitch Stephen Panther

IPC分类号： G06F16/17 ,  F16K31/02 ,  G06F9/32 ,  G06F9/38 ,  G06F9/50 ,  G06F9/54 ,  G06F16/174 ,  G06F16/61

CPC分类号： G06F16/1734 ,  F16K31/02 ,  G06F9/321 ,  G06F9/381 ,  G06F9/3834 ,  G06F9/5016 ,  G06F9/542 ,  G06F9/544 ,  G06F16/1744 ,  G06F16/61

摘要： A control system for a valve or other flow control device can include a processor device. The control system can further include a memory in communication with the processor device. The memory may have a fixed maximum capacity. The control system can further include one or more ports to receive signals corresponding to events for the valve or other flow control device. The processor device can be configured to execute operations that include: over a time interval, counting a quantity of events of a first type, corresponding to the signals received at the one or more ports, and after the time interval, storing in the memory a record of the first type of event over the time interval, based on the counted quantity.

公开(公告)号：US12001845B2

公开(公告)日：2024-06-04

申请号：US17755130

申请日：2020-10-15

申请人： Arm Limited

发明人： Mbou Eyole ,  Stefanos Kaxiras

IPC分类号： G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/384

摘要： An apparatus comprises first instruction execution circuitry, second instruction execution circuitry, and a decoupled access buffer. Instructions of an ordered sequence of instructions are issued to one of the first and second instruction execution circuitry for execution in dependence on whether the instruction has a first type label or a second type label. An instruction with the first type label is an access-related instruction which determines at least one characteristic of a load operation to retrieve a data value from a memory address. Instruction execution by the first instruction execution circuitry of instructions having the first type label is prioritised over instruction execution by the second instruction execution circuitry of instructions having the second type label. Data values retrieved from memory as a result of execution of the first type instructions are stored in the decoupled access buffer.

公开(公告)号：US20240012764A1

公开(公告)日：2024-01-11

申请号：US18472511

申请日：2023-09-22

申请人： Oracle International Corporation

发明人： Maurizio Cimadamore ,  James Malcolm Laskey ,  Jorn Bender Vernee

IPC分类号： G06F9/52 ,  G06F9/38

CPC分类号： G06F9/52 ,  G06F9/3834

摘要： Techniques for transitioning between memory segment views include: instantiating a first memory segment view that confines access to a memory segment to a first thread; receiving a request to transition ownership of the memory segment to a second thread; responsive to receiving the request to transition ownership of the memory segment to the second thread: instantiating a second memory segment view that permits access to the memory segment by the second thread; copying metadata from the first memory segment view to the second memory segment view; terminating the first memory segment view, to prevent access to the memory segment via the first memory segment view.

公开(公告)号：US11868777B2

公开(公告)日：2024-01-09

申请号：US17123270

申请日：2020-12-16

申请人： ADVANCED MICRO DEVICES, INC.

发明人： John Kalamatianos ,  Michael T. Clark ,  Marius Evers ,  William L. Walker ,  Paul Moyer ,  Jay Fleischman ,  Jagadish B. Kotra

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/52

CPC分类号： G06F9/30181 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30138 ,  G06F9/3834 ,  G06F9/3877 ,  G06F9/52

摘要： Processor-guided execution of offloaded instructions using fixed function operations is disclosed. Instructions designated for remote execution by a target device are received by a processor. Each instruction includes, as an operand, a target register in the target device. The target register may be an architected virtual register. For each of the plurality of instructions, the processor transmits an offload request in the order that the instructions are received. The offload request includes the instruction designated for remote execution. The target device may be, for example, a processing-in-memory device or an accelerator coupled to a memory.

公开(公告)号：US11681529B2

公开(公告)日：2023-06-20

申请号：US17410934

申请日：2021-08-24

申请人： Intel Corporation

发明人： Swagath Venkataramani ,  Dipankar Das ,  Sasikanth Avancha ,  Ashish Ranjan ,  Subarno Banerjee ,  Bharat Kaul ,  Anand Raghunathan

IPC分类号： G06F12/14 ,  G06F9/30 ,  G06N3/04 ,  G06N3/084 ,  G06N3/063 ,  G06F9/52 ,  G06F9/38

CPC分类号： G06F9/30145 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/52 ,  G06N3/04 ,  G06N3/063 ,  G06N3/084

摘要： Systems, methods, and apparatuses relating to access synchronization in a shared memory are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, and an execution unit to execute the decoded instruction to: receive a first input operand of a memory address to be tracked and a second input operand of an allowed sequence of memory accesses to the memory address, and cause a block of a memory access that violates the allowed sequence of memory accesses to the memory address. In one embodiment, a circuit separate from the execution unit compares a memory address for a memory access request to one or more memory addresses in a tracking table, and blocks a memory access for the memory access request when a type of access violates a corresponding allowed sequence of memory accesses to the memory address for the memory access request.

公开(公告)号：US10078518B2

公开(公告)日：2018-09-18

申请号：US13666328

申请日：2012-11-01

申请人： International Business Machines Corporation

发明人： Randal C. Swanberg

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3851 ,  G06F9/30123 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/461

摘要： Intelligent context management for thread switching is achieved by determining that a register bank has not been used by a thread for a predetermined number of dispatches, and responsively disabling the register bank for use by that thread. A counter is incremented each time the thread is dispatched but the register bank goes unused. Usage or non-usage of the register bank is inferred by comparing a previous checksum for the register bank to a current checksum. If the previous and current checksums match, the system concludes that the register bank has not been used. If a thread attempts to access a disabled bank, the processor takes an interrupt, enables the bank, and resets the corresponding counter. For a system utilizing transactional memory, it is preferable to enable all of the register banks when thread processing begins to avoid aborted transactions from register banks disabled by lazy context management techniques.

公开(公告)号：US10078515B2

公开(公告)日：2018-09-18

申请号：US13251441

申请日：2011-10-03

申请人： Michael K Gschwind ,  Valentina Salapura

发明人： Michael K Gschwind ,  Valentina Salapura

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/40 ,  G06F9/46

CPC分类号： G06F9/3834 ,  G06F9/30076 ,  G06F9/30105 ,  G06F9/30127 ,  G06F9/30185 ,  G06F9/3832 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/462

摘要： Operand liveness state information is maintained during context switches for current architected operands of executing programs. The current operand state information indicates whether corresponding current operands are enabled or disabled for use by a first program module comprising machine instructions of an instruction set architecture (ISA) for disabling current architected operands. A machine instruction of the first program module accesses a current operand by using the current operand state information to determine whether a previously stored current operand value is accessible by the first program module.