公开(公告)号：US09805447B2

公开(公告)日：2017-10-31

申请号：US13690142

申请日：2012-11-30

Applicant: ARM Limited

Inventor： Andreas Engh-halstvedt ,  Jorn Nystad ,  Frode Heggelund ,  Ronny Pedersen

IPC: G06T5/00 ,  G06T15/50 ,  G06T11/40

CPC classification number: G06T5/002 ,  G06T11/40 ,  G06T15/503 ,  G06T2200/28

Abstract: When carrying out a second, higher level of anti-aliasing such as 8×MSAA, in a graphics processing pipeline 1 configured to “natively” support a first level of anti-aliasing, such as 4×MSAA, the rasterization stage 3, early Z (depth) and stencil test stage 4, late Z (depth) and stencil test stage 7, blending stage 9, and downsampling and writeback (multisample resolve) stage 11 of the graphics processing pipeline 1 process each graphics fragment or pixel that they receive for processing in plural processing passes, each such processing pass processing a sub-set of the sampling points that the fragment represents, but the fragment shader 6 is configured to process each graphics fragment in a processing pass that processes all the sampling points that the fragment represents in parallel, so as to ensure compliance with the desired higher level of multisampled anti-aliasing.

公开(公告)号：US09672035B2

公开(公告)日：2017-06-06

申请号：US14504947

申请日：2014-10-02

Applicant: ARM LIMITED

Inventor： Ronny Pedersen

IPC: G06F15/76 ,  G06F15/00 ,  G06F9/30 ,  G06F15/80

CPC classification number: G06F9/30036 ,  G06F15/8053

Abstract: A data processing apparatus and method are provided for processing execution threads, where each execution thread specifies at least one instruction. The data processing apparatus has a vector processing unit providing a plurality M of lanes of parallel processing, within each lane the vector processing unit being configured to perform a processing operation on a data element input to that lane for each of one or more input operands. A vector instruction is received that is specified by a group of the execution threads, that vector instruction identifying an associated processing operation and also providing an indication of the data elements of each input operand that are to be subjected to that associated processing operation. Vector merge circuitry then determines, based on that information, a required number of lanes of parallel processing for performing the associated processing operation. If it is determined that the required number of lanes is less than or equal to half the available number of lanes within the vector processing unit, then the vector merge circuitry allocates a plurality of the execution threads of the group to the vector processing unit such that each execution thread in that plurality is allocated different lanes amongst the available lanes of parallel processing. As a result, the vector processing unit then performs the associated processing operation in parallel for each of the plurality of execution threads, significantly increasing performance.

公开(公告)号：US20130141445A1

公开(公告)日：2013-06-06

申请号：US13690142

申请日：2012-11-30

Applicant: ARM Limited

Inventor： Andreas Engh-halstvedt ,  Jorn Nystad ,  Frode Heggelund ,  Ronny Pedersen

IPC: G06T5/00

CPC classification number: G06T5/002 ,  G06T11/40 ,  G06T15/503 ,  G06T2200/28

Abstract: When carrying out a second, higher level of anti-aliasing such as 8× MSAA, in a graphics processing pipeline 1 configured to “natively” support a first level of anti-aliasing, such as 4× MSAA, the rasterisation stage 3, early Z (depth) and stencil test stage 4, late Z (depth) and stencil test stage 7, blending stage 9, and downsampling and writeback (multisample resolve) stage 11 of the graphics processing pipeline 1 process each graphics fragment or pixel that they receive for processing in plural processing passes, each such processing pass processing a sub-set of the sampling points that the fragment represents, but the fragment shader 6 is configured to process each graphics fragment in a processing pass that processes all the sampling points that the fragment represents in parallel, so as to ensure compliance with the desired higher level of multisampled anti-aliasing.

Abstract translation: 在图形处理流水线1中执行第二次更高水平的抗锯齿（例如8×MSAA），该图形处理管线1被配置为“本地地”支持第一水平的抗锯齿，例如4×MSAA，光栅化阶段3，早 Z（深度）和模板测试阶段4，后期Z（深度）和模板测试阶段7，混合阶段9和图形处理流水线1的下采样和回写（多采样分辨）阶段11处理它们接收的每个图形片段或像素 为了在多个处理通道中进行处理，每个这样的处理通过处理片段表示的采样点的子集，但是片段着色器6被配置为在处理所有采样点的处理通过中处理每个图形片段，片段 并行表示，以确保符合所需的更高级别的多采样抗锯齿。