公开(公告)号：US20130141445A1

公开(公告)日：2013-06-06

申请号：US13690142

申请日：2012-11-30

Applicant: ARM Limited

Inventor： Andreas Engh-halstvedt ,  Jorn Nystad ,  Frode Heggelund ,  Ronny Pedersen

IPC: G06T5/00

CPC classification number: G06T5/002 ,  G06T11/40 ,  G06T15/503 ,  G06T2200/28

Abstract: When carrying out a second, higher level of anti-aliasing such as 8× MSAA, in a graphics processing pipeline 1 configured to “natively” support a first level of anti-aliasing, such as 4× MSAA, the rasterisation stage 3, early Z (depth) and stencil test stage 4, late Z (depth) and stencil test stage 7, blending stage 9, and downsampling and writeback (multisample resolve) stage 11 of the graphics processing pipeline 1 process each graphics fragment or pixel that they receive for processing in plural processing passes, each such processing pass processing a sub-set of the sampling points that the fragment represents, but the fragment shader 6 is configured to process each graphics fragment in a processing pass that processes all the sampling points that the fragment represents in parallel, so as to ensure compliance with the desired higher level of multisampled anti-aliasing.

Abstract translation: 在图形处理流水线1中执行第二次更高水平的抗锯齿（例如8×MSAA），该图形处理管线1被配置为“本地地”支持第一水平的抗锯齿，例如4×MSAA，光栅化阶段3，早 Z（深度）和模板测试阶段4，后期Z（深度）和模板测试阶段7，混合阶段9和图形处理流水线1的下采样和回写（多采样分辨）阶段11处理它们接收的每个图形片段或像素 为了在多个处理通道中进行处理，每个这样的处理通过处理片段表示的采样点的子集，但是片段着色器6被配置为在处理所有采样点的处理通过中处理每个图形片段，片段 并行表示，以确保符合所需的更高级别的多采样抗锯齿。

公开(公告)号：US09805447B2

公开(公告)日：2017-10-31

申请号：US13690142

申请日：2012-11-30

Applicant: ARM Limited

Inventor： Andreas Engh-halstvedt ,  Jorn Nystad ,  Frode Heggelund ,  Ronny Pedersen

IPC: G06T5/00 ,  G06T15/50 ,  G06T11/40

CPC classification number: G06T5/002 ,  G06T11/40 ,  G06T15/503 ,  G06T2200/28

Abstract: When carrying out a second, higher level of anti-aliasing such as 8×MSAA, in a graphics processing pipeline 1 configured to “natively” support a first level of anti-aliasing, such as 4×MSAA, the rasterization stage 3, early Z (depth) and stencil test stage 4, late Z (depth) and stencil test stage 7, blending stage 9, and downsampling and writeback (multisample resolve) stage 11 of the graphics processing pipeline 1 process each graphics fragment or pixel that they receive for processing in plural processing passes, each such processing pass processing a sub-set of the sampling points that the fragment represents, but the fragment shader 6 is configured to process each graphics fragment in a processing pass that processes all the sampling points that the fragment represents in parallel, so as to ensure compliance with the desired higher level of multisampled anti-aliasing.

公开(公告)号：US09122646B2

公开(公告)日：2015-09-01

申请号：US13623744

申请日：2012-09-20

Applicant: ARM Limited

Inventor： Sean Ellis ,  Andreas Engh-halstvedt ,  Jorn Nystad

IPC: G06T1/20 ,  G06T11/40 ,  G06F15/16 ,  G06F9/50

CPC classification number: G06F15/16 ,  G06F9/5083 ,  G06T1/20 ,  G06T11/40

Abstract: In a tile-based graphics processing system having plural rendering processors, the set of tiles 31 to be processed to generate an output frame 30 for display is partitioned among the different rendering processors by defining respective tile traversal paths 32, 33, 34, 35 for each rendering processor that start at a tile initially allocated to the processor and that, at least for the initial tiles along the path, traverse to spatially adjacent tiles in the output, and that will traverse every tile to be rendered if followed to their end. The next tile for a given rendering processor to process is then selected as being the next tile along its defined path, unless the next tile in the path has already been processed (or is already being processed) by another rendering processor, in which case the next tile to be allocated to the rendering processor is selected to be a free tile further on in the tile traversal path for that processor.

Abstract translation: 在具有多个渲染处理器的基于瓦片的图形处理系统中，要处理以生成用于显示的输出帧30的瓦片组31在不同的渲染处理器之间通过定义相应的瓦片穿越路径32,33,34,35进行划分，用于 每个渲染处理器从最初分配给处理器的瓦片开始，并且至少对于沿着路径的初始瓦片，遍历输出中的空间相邻的瓦片，并且如果跟随到它们的结尾，则遍历要渲染的每个瓦片。 然后，将待处理的给定渲染处理器的下一个图块选择为沿其定义的路径的下一个图块，除非路径中的下一个图块已经被另一个渲染处理器处理（或已被处理），在这种情况下 将要分配给渲染处理器的下一个瓦片选择为该处理器的瓦片穿越路径中的另外的空闲瓦片。

公开(公告)号：US20130076761A1

公开(公告)日：2013-03-28

申请号：US13623744

申请日：2012-09-20

Applicant: ARM Limited

Inventor： Sean Ellis ,  Andreas Engh-halstvedt ,  Jorn Nystad

IPC: G06F15/16

CPC classification number: G06F15/16 ,  G06F9/5083 ,  G06T1/20 ,  G06T11/40

Abstract: In a tile-based graphics processing system having plural rendering processors, the set of tiles 31 to be processed to generate an output frame 30 for display is partitioned among the different rendering processors by defining respective tile traversal paths 32, 33, 34, 35 for each rendering processor that start at a tile initially allocated to the processor and that, at least for the initial tiles along the path, traverse to spatially adjacent tiles in the output, and that will traverse every tile to be rendered if followed to their end. The next tile for a given rendering processor to process is then selected as being the next tile along its defined path, unless the next tile in the path has already been processed (or is already being processed) by another rendering processor, in which case the next tile to be allocated to the rendering processor is selected to be a free tile further on in the tile traversal path for that processor.

Abstract translation: 在具有多个渲染处理器的基于瓦片的图形处理系统中，要处理以生成用于显示的输出帧30的瓦片组31在不同的渲染处理器之间通过定义相应的瓦片穿越路径32,33,34,35进行划分，用于 每个渲染处理器从最初分配给处理器的瓦片开始，并且至少对于沿着路径的初始瓦片，遍历输出中的空间相邻的瓦片，并且如果跟随到它们的结尾，则遍历要渲染的每个瓦片。 然后，将待处理的给定渲染处理器的下一个图块选择为沿其定义的路径的下一个图块，除非路径中的下一个图块已经被另一个渲染处理器处理（或已被处理），在这种情况下 将要分配给渲染处理器的下一个瓦片选择为该处理器的瓦片穿越路径中的另外的空闲瓦片。