公开(公告)号：US3930199A

公开(公告)日：1975-12-30

申请号：US53778274

申请日：1974-12-31

Applicant: ASEA AB

Inventor： VALIS JAROSLAV

IPC: G01P3/489 ,  G01R23/10 ,  G01R23/02

CPC classification number: G01R23/10 ,  G01P3/489

Abstract: An arrangement for measuring frequency includes a counter unit and two multipliers connected in series with each other to the counter unit. A sensing unit senses each pulse in an unknown pulse train, the frequency of which is to be determined. The multipliers form a second pulse train, the frequency of which is proportional to the square of the content of the counter unit. The counter unit reduces its content by a predetermined amount for each pulse in the second pulse train. The sensing unit delivers a third pulse train to the counter unit, which causes the counter unit to preset its content to a predetermined maximum quantity. The content of the counter unit at the time of each pulse in the first pulse train indicates the frequency of the first pulse train.

Abstract translation: 用于测量频率的装置包括计数器单元和彼此串联连接的两个乘法器到计数器单元。 感测单元感测未知脉冲串中的每个脉冲，其频率将被确定。 乘法器形成第二脉冲序列，其频率与计数器单元的内容的平方成比例。 计数器单元将第二脉冲列中的每个脉冲的内容减少预定量。 感测单元将第三脉冲串传送到计数器单元，这使得计数器单元将其内容预设为预定的最大量。 第一脉冲列中的每个脉冲时的计数器单元的内容表示第一脉冲序列的频率。

公开(公告)号：US3928798A

公开(公告)日：1975-12-23

申请号：US51262474

申请日：1974-10-07

Applicant: ASEA AB

Inventor： VALIS JAROSLAV

IPC: G01P3/489 ,  G01R23/10 ,  G01R23/02

CPC classification number: G01P3/489 ,  G01R23/10

Abstract: An arrangement for frequency/digital conversion, particularly for digital revolution and speed measuring, includes a clock unit, a control unit, and a counter unit. The clock unit provides a pulse train with a constant frequency. A multiplying unit is provided which gives a second pulse train, the frequency of which is dependent on the product of the constant frequency and the latest maximum value of the contents of the counter unit. The contents of the counter unit are reduced by a first quantity upon each pulse of the second pulse train. Another unit is arranged to supply the control unit with a third pulse train with an unknown frequency. The control unit emits a control signal to the counter unit for each pulse in the third pulse train. The counter unit increases its contents by a second quantity at the occurrence of such control signal. The second quantity is greater than or equal to the first quantity. After each such addition, the contents of the counter unit reach a new maximum value which constitutes a digital representation of the frequency of the second pulse train.

Abstract translation: 用于频率/数字转换的装置，特别是用于数字转速和速度测量的装置包括时钟单元，控制单元和计数器单元。 时钟单元提供具有恒定频率的脉冲串。 提供一个乘法单元，其给出第二脉冲串，其频率取决于计数器单元的内容的恒定频率和最新最大值的乘积。 在第二脉冲串的每个脉冲上，计数器单元的内容减少第一量。 另一个单元被布置成向控制单元提供具有未知频率的第三脉冲串。 控制单元对第三脉冲串中的每个脉冲向计数器单元发出控制信号。 在发生这种控制信号时，计数器单元将其内容增加第二数量。 第二数量大于或等于第一数量。 在每次这样的添加之后，计数器单元的内容达到新的最大值，其构成第二脉冲序列的频率的数字表示。