公开(公告)号：US20130332744A1

公开(公告)日：2013-12-12

申请号：US13910476

申请日：2013-06-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Gongyuan Zhuang

IPC: G06F21/72

CPC classification number: G06F21/72 ,  G09C1/00 ,  H04L9/0631 ,  H04L9/0637 ,  H04L9/0643 ,  H04L9/3066 ,  H04L2209/125

Abstract: A method, an apparatus, and a non-transitory computer readable medium for accelerating cryptographic processing are presented. A cryptographic algorithm is parallelized, which includes breaking the cryptographic algorithm into components, parallelizing an entire component if the component is fully parallelizable, parallelizing part of a component if the component is partially parallelizable, and sequentially executing a component if the component is not parallelizable. Processing of the parallelizable component or the partially parallelizable component is distributed to one or more parallelized devices. The parallelized devices include at least one of: a graphics processing unit or a cryptographic processing device, which may include an integrated cryptographic processor or a cryptographic co-processor.

Abstract translation: 提出了一种用于加速加密处理的方法，装置和非暂时性计算机可读介质。 一种加密算法并行化，其中包括将加密算法分解为组件，如果组件完全可并行化，则将整个组件并行化，如果组件部分可并行化，则将组件的一部分并行化，如果组件不可并行化，则依次执行组件。 可并行化部件或部分可并行化部件的处理被分配到一个或多个并联装置。 并行化设备包括以下至少一个：图形处理单元或密码处理设备，其可以包括集成密码处理器或密码协处理器。

公开(公告)号：US09342712B2

公开(公告)日：2016-05-17

申请号：US13910476

申请日：2013-06-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Gongyuan Zhuang

IPC: G06F21/72 ,  G09C1/00 ,  H04L9/06 ,  H04L9/30

CPC classification number: G06F21/72 ,  G09C1/00 ,  H04L9/0631 ,  H04L9/0637 ,  H04L9/0643 ,  H04L9/3066 ,  H04L2209/125

Abstract: A method, an apparatus, and a non-transitory computer readable medium for accelerating cryptographic processing are presented. A cryptographic algorithm is parallelized, which includes breaking the cryptographic algorithm into components, parallelizing an entire component if the component is fully parallelizable, parallelizing part of a component if the component is partially parallelizable, and sequentially executing a component if the component is not parallelizable. Processing of the parallelizable component or the partially parallelizable component is distributed to one or more parallelized devices. The parallelized devices include at least one of: a graphics processing unit or a cryptographic processing device, which may include an integrated cryptographic processor or a cryptographic co-processor.

Abstract translation: 提出了一种用于加速加密处理的方法，装置和非暂时性计算机可读介质。 一种加密算法并行化，其中包括将加密算法分解为组件，如果组件完全可并行化，则将整个组件并行化，如果组件部分可并行化，则将组件的一部分并行化，如果组件不可并行化，则依次执行组件。 可并行化部件或部分可并行化部件的处理被分配到一个或多个并联装置。 并行化设备包括以下至少一个：图形处理单元或密码处理设备，其可以包括集成密码处理器或密码协处理器。

公开(公告)号：US10523428B2

公开(公告)日：2019-12-31

申请号：US15820539

申请日：2017-11-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Gongyuan Zhuang ,  Thomas R. Woller

IPC: H04L9/08 ,  H04L9/14 ,  H04L9/30

Abstract: A method and apparatus provides cryptographic keys using, for example, a cryptographic co-processor (CCP) that uses spare processor cycles to work on cryptographic key generation in advance of the keys being needed by a requestor such as an application, or other process in the device. In one example, the cryptographic co-processor detects an idle condition of the CCP such as an idle condition of a cryptographic engine in the CCP. Control logic causes the CCP to generate at least one asymmetric key component corresponding to an asymmetric cryptographic key in response to detecting the idle condition. The method and apparatus stores the asymmetric key component(s) in persistent memory and generates the asymmetric cryptographic key using the stored asymmetric key component that was generated in response to detection of the idle condition of the CCP.

公开(公告)号：US20190158278A1

公开(公告)日：2019-05-23

申请号：US15820539

申请日：2017-11-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Gongyuan Zhuang ,  Thomas R. Woller

IPC: H04L9/08 ,  H04L9/14

CPC classification number: H04L9/0822 ,  H04L9/0861 ,  H04L9/0877 ,  H04L9/0894 ,  H04L9/0897 ,  H04L9/14 ,  H04L9/302 ,  H04L9/3033

Abstract: A method and apparatus provides cryptographic keys using, for example, a cryptographic co-processor (CCP) that uses spare processor cycles to work on cryptographic key generation in advance of the keys being needed by a requestor such as an application, or other process in the device. In one example, the cryptographic co-processor detects an idle condition of the CCP such as an idle condition of a cryptographic engine in the CCP. Control logic causes the CCP to generate at least one asymmetric key component corresponding to an asymmetric cryptographic key in response to detecting the idle condition. The method and apparatus stores the asymmetric key component(s) in persistent memory and generates the asymmetric cryptographic key using the stored asymmetric key component that was generated in response to detection of the idle condition of the CCP.