公开(公告)号：US20210158855A1

公开(公告)日：2021-05-27

申请号：US16692714

申请日：2019-11-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Arijit Banerjee ,  Russell Schreiber ,  Kyle Whittle

IPC: G11C11/4091 ,  G11C11/419 ,  G11C11/4074 ,  G11C7/10

Abstract: A read path for reading data from a memory includes a sense amplifier having data (SAT) and data complement (SAC) output nodes and a latch. The latch includes an input tri-state inverter including first and second PMOS transistors connected between VDD and an intermediate node, and first and second NMOS transistors connected between VSS and the intermediate node. A gate connection of the first PMOS and NMOS transistors is connected to the SAT node; a gate connection of the second PMOS transistor is connected to a sense amplifier enable complement input; and a gate connection of the second NMOS transistor is connected to a sense amplifier enable input. The latch also includes an output driver with an input connected to the intermediate node and an output connected to a data output node. The latch thus has two gate delays between the SAT node and the data output node.

公开(公告)号：US11227651B2

公开(公告)日：2022-01-18

申请号：US16692714

申请日：2019-11-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Arijit Banerjee ,  Russell Schreiber ,  Kyle Whittle

IPC: G11C7/00 ,  G11C11/4091 ,  G11C11/419 ,  G11C7/10 ,  G11C11/4074

Abstract: A read path for reading data from a memory includes a sense amplifier having data (SAT) and data complement (SAC) output nodes and a latch. The latch includes an input tri-state inverter including first and second PMOS transistors connected between VDD and an intermediate node, and first and second NMOS transistors connected between VSS and the intermediate node. A gate connection of the first PMOS and NMOS transistors is connected to the SAT node; a gate connection of the second PMOS transistor is connected to a sense amplifier enable complement input; and a gate connection of the second NMOS transistor is connected to a sense amplifier enable input. The latch also includes an output driver with an input connected to the intermediate node and an output connected to a data output node. The latch thus has two gate delays between the SAT node and the data output node.