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公开(公告)号：US20240202003A1
公开(公告)日：2024-06-20
申请号：US18066115
申请日：2022-12-14
Applicant: Advanced Micro Devices, Inc.
Inventor： Matthäus G. Chajdas , Michael J. Mantor , Rex Eldon McCrary , Christopher J. Brennan , Robert Martin , Brian Kenneth Bennett
CPC classification number: G06F9/3867 , G06F9/4881
Abstract: Systems, apparatuses, and methods for implementing a hierarchical scheduling in fixed-function graphics pipeline are disclosed. In various implementations, a processor includes a pipeline comprising a plurality of fixed-function units and a scheduler. The scheduler is configured to schedule a first operation for execution by one or more fixed-function units of the pipeline by scheduling the first operation with a first unit of the pipeline, responsive to a first mode of operation and schedule a second operation for execution by a selected fixed-function unit of the pipeline by scheduling the second operation directly to the selected fixed-function unit, independent of a sequential arrangement of the one or more fixed-function units in the pipeline, responsive to a second mode of operation.
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公开(公告)号：US20240111575A1
公开(公告)日：2024-04-04
申请号：US17936798
申请日：2022-09-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Matthäus G. Chajdas , Michael J. Mantor , Rex Eldon McCrary , Christopher J. Brennan , Robert Martin , Dominik Baumeister , Fabian Robert Sebastian Wildgrube
CPC classification number: G06F9/4881 , G06F9/546
Abstract: Systems, apparatuses, and methods for implementing a message passing system to schedule work in a computing system. In various implementations, a processor includes a global scheduler, and a plurality of local schedulers with each of the local schedulers coupled to a plurality of processors. The processor further includes a shared cache that is shared by the plurality of local schedulers. Also, a plurality of mailboxes are implemented to enable communication between the local schedulers and the global scheduler. To schedule work items for execution, the global scheduler is configured to store one or more work items in the shared cache and store an indication in a mailbox for a first local scheduler of the plurality of local schedulers. Responsive to detecting the message in the mailbox, the first local scheduler identifies a location of the one or more work items in the shared cache and retrieves them for scheduling locally.
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公开(公告)号：US20240111574A1
公开(公告)日：2024-04-04
申请号：US17936788
申请日：2022-09-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Matthäus G. Chajdas , Michael J. Mantor , Rex Eldon McCrary , Christopher J. Brennan , Robert Martin , Dominik Baumeister , Fabian Robert Sebastian Wildgrube
CPC classification number: G06F9/4881 , G06F11/3024 , G06F11/3055
Abstract: Systems, apparatuses, and methods for implementing a hierarchical scheduler. In various implementations, a processor includes a global scheduler, and a plurality of independent local schedulers with each of the local schedulers coupled to a plurality of processors. In one implementation, the processor is a graphics processing unit and the processors are computation units. The processor further includes a shared cache that is shared by the plurality of local schedulers. Each of the local schedulers also includes a local cache used by the local scheduler and processors coupled to the local scheduler. To schedule work items for execution, the global scheduler is configured to store one or more work items in the shared cache and convey an indication to a first local scheduler of the plurality of local schedulers which causes the first local scheduler to retrieve the one or more work items from the shared cache. Subsequent to retrieving the work items, the local scheduler is configured to schedule the retrieved work items for execution by the coupled processors. Each of the plurality of local schedulers is configured to schedule work items for execution independent of scheduling performed by other local schedulers.
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