公开(公告)号：US6022762A

公开(公告)日：2000-02-08

申请号：US368559

申请日：1999-08-05

Applicant: Alberto Perelli

Inventor： Alberto Perelli

IPC: H01L21/31 ,  H01L21/316 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532 ,  H01L21/56 ,  H01L21/60

CPC classification number: H01L23/564 ,  H01L23/3171 ,  H01L23/5329 ,  H01L2924/0002

Abstract: A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material includes formation above an intermediate process structure of a dielectric multilayer comprising a layer of amorphous planarizing material. The process also includes the partial removal of the dielectric multilayer so as to create at least one peripheral termination of the multilayer in the device edge morphological structure. Removal of the dielectric multilayer requires that the peripheral termination thereof be located in a zone of the intermediate process structure relatively higher than the level of the major surface, if compared with adjacent zones of the intermediate structure itself at least internally toward the circuit and in so far as to the device edge morphological structure.

Abstract translation: 用于形成用于在周围保护和密封集成在半导体材料的衬底的主表面中的电子电路的器件边缘形态结构的方法包括在包含非晶平坦化材料层的电介质多层的中间工艺结构之上形成。 该方法还包括部分去除电介质多层，以便在器件边缘形态结构中产生多层的至少一个外围终端。 如果与中间结构本身的相邻区域至少在内部朝向电路相比，去除电介质多层体需要其外围终端位于相对高于主表面的水平的中间工艺结构的区域中，并且如此 至于器件边缘的形态结构。

公开(公告)号：US5969408A

公开(公告)日：1999-10-19

申请号：US14364

申请日：1998-01-27

Applicant: Alberto Perelli

Inventor： Alberto Perelli

IPC: H01L21/31 ,  H01L21/316 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532 ,  H01L23/544 ,  H01L23/58 ,  H01L29/06

CPC classification number: H01L23/564 ,  H01L23/3171 ,  H01L23/5329 ,  H01L2924/0002

Abstract: A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material includes formation above an intermediate process structure of a dielectric multilayer comprising a layer of amorphous planarizing material. The process also includes the partial removal of the dielectric multilayer so as to create at least one peripheral termination of the multilayer in the device edge morphological structure. Removal of the dielectric multilayer requires that the peripheral termination thereof be located in a zone of the intermediate process structure relatively higher than the level of the major surface, if compared with adjacent zones of the intermediate structure itself at least internally toward the circuit and in so far as to the device edge morphological structure.

Abstract translation: 用于形成用于在周围保护和密封集成在半导体材料的衬底的主表面中的电子电路的器件边缘形态结构的方法包括在包含非晶平坦化材料层的电介质多层的中间工艺结构之上形成。 该方法还包括部分去除电介质多层，以便在器件边缘形态结构中产生多层的至少一个外围终端。 如果与中间结构本身的相邻区域至少在内部朝向电路相比，去除电介质多层体需要其外围终端位于相对高于主表面的水平的中间工艺结构的区域中，并且如此 至于器件边缘的形态结构。