公开(公告)号：US12260214B1

公开(公告)日：2025-03-25

申请号：US17937332

申请日：2022-09-30

Applicant: Amazon Technologies, Inc.

Inventor： Paul Gilbert Meyer ,  Ron Diamant ,  Sundeep Amirineni ,  Sunil Kumar Bathula

IPC: G06F9/38 ,  G06F9/30 ,  G06F13/16

Abstract: A compute channel can have multiple computational circuit blocks coupled in series to form a pipeline. The compute channel can perform a computation on an input tensor to generate an output tensor based on an instruction. When the computational does not require all of the computational circuit blocks, the throughput of the compute channel can be increased by splitting the data elements of the input tensor into multiple input data streams. The multiple input data streams are provided to respective subsets of one or more computational circuit blocks in the pipeline using bypass circuitry of the computational circuit blocks, and the computation can be performed on multiple input data streams in the respective subsets of one or more computational circuit blocks to generate multiple output data streams corresponding to the output tensor.