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公开(公告)号：US20160334818A1
公开(公告)日：2016-11-17
申请号：US14713312
申请日：2015-05-15
Applicant: Analog Devices Global
Inventor： Amit Kumar Singh , Nitish Kuttan , Sriram Ganesan
IPC: G05F1/56
CPC classification number: G05F1/56
Abstract: A regulator circuit can include a cascaded topology, comprising a first integrated low-dropout (LDO) regulator circuit having a supply node, the first integrated LDO regulator circuit configured to provide a first loop bandwidth and configured to provide a regulated first output voltage to an intermediate node using energy provided by the supply node, and a second integrated LDO regulator circuit having an input coupled to the intermediate node, the second LDO regulator circuit configured to provide a second loop bandwidth and configured to provide a regulated second output voltage to an output node, where the second loop bandwidth is narrower than the first loop bandwidth. The regulator circuit need not require an external capacitor. The regulator circuit can be used to provide one or more of enhanced power supply rejection and noise performance.
Abstract translation: 调节器电路可以包括级联拓扑，其包括具有供电节点的第一集成低压差（LDO）调节器电路，所述第一集成LDO调节器电路被配置为提供第一环路带宽并且被配置为将调节的第一输出电压提供给 中间节点使用由所述供应节点提供的能量，以及第二集成LDO调节器电路，其具有耦合到所述中间节点的输入，所述第二LDO调节器电路被配置为提供第二环路带宽并且被配置为向输出端提供调节的第二输出电压 节点，其中第二环路带宽比第一环路带宽窄。 调节器电路不需要外部电容器。 调节器电路可用于提供增强的电源抑制和噪声性能中的一个或多个。
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公开(公告)号：US10790740B2
公开(公告)日：2020-09-29
申请号：US15968981
申请日：2018-05-02
Applicant: Analog Devices Global Unlimited Company
Inventor： Amit Kumar Singh , Sriram Ganesan , Miguel A. Ruiz , Jose Tejada
Abstract: Techniques for improving efficiency of a switched-capacitor voltage regulator are provided. In an example, a switched-capacitor voltage regulator can include a switched-capacitor network having multiple gain configurations, a clock configured to switch capacitors of the switched-capacitor network between a charge state and a discharge state to provide a scaled output voltage, and a controller configured to select a capacitor configuration associated with a gain of the multiple gain configurations to provide the scaled output voltage within a desired output voltage range while continuously switching the capacitor configuration, and to interrupt switching of the capacitor configuration to permit an output voltage of the switched-capacitor voltage regulator to fall below the scaled output voltage but to remain above a lower limit of the desired output voltage range to save power by reducing losses due to the switching.
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Patent Agency Ranking
公开(公告)号：US10509426B2
公开(公告)日：2019-12-17
申请号：US15969204
申请日：2018-05-02
Applicant: Analog Devices Global Unlimited Company
Inventor： Sriram Ganesan , Amit Kumar Singh , Nilanjan Pal , Nitish Kuttan
IPC: G05F1/46 , G01R19/00 , G11C11/417
Abstract: Methods, systems and circuits for controlling the power available to the load, by reducing the power available to the load, and additionally or alternatively, limiting the current available by pre-establishing a maximum reference current. The reference current is compared to the actual or estimated current drawn by the load or part of the load. The comparison result is used to control a device or switch which disconnects the power supply or power supply regulator, whether connected directly to the load or connected via voltage dropping device, to one or more or a plurality of the load blocks when the maximum current is exceeded.
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公开(公告)号：US09665112B2
公开(公告)日：2017-05-30
申请号：US14713312
申请日：2015-05-15
Applicant: Analog Devices Global
Inventor： Amit Kumar Singh , Nitish Kuttan , Sriram Ganesan
IPC: G05F1/56
CPC classification number: G05F1/56
Abstract: A regulator circuit can include a cascaded topology, comprising a first integrated low-dropout (LDO) regulator circuit having a supply node, the first integrated LDO regulator circuit configured to provide a first loop bandwidth and configured to provide a regulated first output voltage to an intermediate node using energy provided by the supply node, and a second integrated LDO regulator circuit having an input coupled to the intermediate node, the second LDO regulator circuit configured to provide a second loop bandwidth and configured to provide a regulated second output voltage to an output node, where the second loop bandwidth is narrower than the first loop bandwidth. The regulator circuit need not require an external capacitor. The regulator circuit can be used to provide one or more of enhanced power supply rejection and noise performance.
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公开(公告)号：US20190341844A1
公开(公告)日：2019-11-07
申请号：US15968981
申请日：2018-05-02
Applicant: Analog Devices Global Unlimited Company
Inventor： Amit Kumar Singh , Sriram Ganesan , Miguel A. Ruiz , Jose Tejada
IPC: H02M3/07
Abstract: Techniques for improving efficiency of a switched-capacitor voltage regulator are provided. In an example, a switched-capacitor voltage regulator can include a switched-capacitor network having multiple gain configurations, a clock configured to switch capacitors of the switched-capacitor network between a charge state and a discharge state to provide a scaled output voltage, and a controller configured to select a capacitor configuration associated with a gain of the multiple gain configurations to provide the scaled output voltage within a desired output voltage range while continuously switching the capacitor configuration, and to interrupt switching of the capacitor configuration to permit an output voltage of the switched-capacitor voltage regulator to fall below the scaled output voltage but to remain above a lower limit of the desired output voltage range to save power by reducing losses due to the switching.
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公开(公告)号：US10312902B2
公开(公告)日：2019-06-04
申请号：US15337587
申请日：2016-10-28
Applicant: Analog Devices Global
Inventor： Amit Kumar Singh , Sriram Ganesan
Abstract: This application discusses techniques for providing a power-on reset (POR) circuit. The techniques take advantage of the small size of active devices, consume very little current and can use a native NMOS transistor to provide a stable reference over temperature and voltage variations.
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公开(公告)号：US20180123583A1
公开(公告)日：2018-05-03
申请号：US15337587
申请日：2016-10-28
Applicant: Analog Devices Global
Inventor： Amit Kumar Singh , Sriram Ganesan
IPC: H03K17/22
CPC classification number: H03K17/223 , H03K2217/0036
Abstract: This application discusses techniques for providing a power-on reset (POR) circuit. The techniques take advantage of the small size of active devices, consume very little current and can use a native NMOS transistor to provide a stable reference over temperature and voltage variations.
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