公开(公告)号：US20160118959A1

公开(公告)日：2016-04-28

申请号：US14719241

申请日：2015-05-21

Applicant: Analog Devices Global

Inventor： Yusuf Alperen Atesal ,  Peter J. Katzin

IPC: H03H11/24

CPC classification number: H03H11/245 ,  H03H7/25

Abstract: Apparatus and methods for reducing glitches in digital step attenuators are disclosed. By configuring a multi-bit DSA such that an attenuation control block changes a plurality of control signals in a manner sequencing individual switches of the DSA, glitches can be reduced and RF signal behavior can be enhanced. The sequence, based upon a unit time delay, causes the transient attenuation value to be bounded between a minimum and maximum and can improve settling time.

Abstract translation: 公开了用于减少数字步进衰减器中的毛刺的装置和方法。 通过配置多比特DSA，使得衰减控制块以对DSA的各个交换机进行排序的方式改变多个控制信号，可以减少毛刺并且可以提高RF信号行为。 该序列基于单位时间延迟，导致瞬态衰减值在最小和最大值之间的界限，并可以提高建立时间。

公开(公告)号：US09548722B2

公开(公告)日：2017-01-17

申请号：US14719241

申请日：2015-05-21

Applicant: Analog Devices Global

Inventor： Yusuf Alperen Atesal ,  Peter J. Katzin

IPC: H03H11/24 ,  H03H7/25

CPC classification number: H03H11/245 ,  H03H7/25

Abstract: Apparatus and methods for reducing glitches in digital step attenuators are disclosed. By configuring a multi-bit DSA such that an attenuation control block changes a plurality of control signals in a manner sequencing individual switches of the DSA, glitches can be reduced and RF signal behavior can be enhanced. The sequence, based upon a unit time delay, causes the transient attenuation value to be bounded between a minimum and maximum and can improve settling time.

Abstract translation: 公开了用于减少数字步进衰减器中的毛刺的装置和方法。 通过配置多比特DSA，使得衰减控制块以对DSA的各个交换机进行排序的方式改变多个控制信号，可以减少毛刺并且可以提高RF信号行为。 该序列基于单位时间延迟，导致瞬态衰减值在最小和最大值之间的界限，并可以提高建立时间。