公开(公告)号：US07447966B2

公开(公告)日：2008-11-04

申请号：US11030349

申请日：2005-01-05

申请人： Anand V. Kamannavar ,  Nathan Dirk Zelle ,  Bradley Forrest Bass ,  Sahir Shiraz Hoda ,  Erich Matthew Gens

发明人： Anand V. Kamannavar ,  Nathan Dirk Zelle ,  Bradley Forrest Bass ,  Sahir Shiraz Hoda ,  Erich Matthew Gens

IPC分类号： G06F11/00

CPC分类号： G06F17/5022

摘要： Exemplary techniques for verifying a hardware design are described. In a described embodiment, a method comprises compiling an error verification object corresponding to an error verification command to verify a portion of a hardware design of a device under test. The error verification object is compiled in accordance with data provided by an error scripting module. The error scripting module has access to hardware-specific data corresponding to the hardware design of the device under test. The compiled object is sent to the device under test and a response to the compiled object is received from the device under test. The received response from the device under test is parsed in accordance with data provided by the error scripting module.

摘要翻译： 描述用于验证硬件设计的示例性技术。 在描述的实施例中，一种方法包括编译与错误验证命令对应的错误验证对象，以验证被测设备的硬件设计的一部分。 错误验证对象是根据错误脚本模块提供的数据进行编译的。 错误脚本模块可以访问与被测设备的硬件设计相对应的硬件特定数据。 编译对象被发送到被测设备，并从被测设备接收到对编译对象的响应。 根据错误脚本编写模块提供的数据，解析来自被测设备的响应。