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公开(公告)号:US20090077290A1
公开(公告)日:2009-03-19
申请号:US12212114
申请日:2008-09-17
Applicant: Anthony Craig DOLWIN
Inventor: Anthony Craig DOLWIN
IPC: G06F13/00
CPC classification number: G06F1/3203 , G06F1/324 , G06F9/30083 , Y02D10/126
Abstract: A computer apparatus comprises a master module and a slave module such that the master module is able to send a functional request to the slave module for the execution by the slave module of a requested function. The master module comprises dynamic voltage scaling (DVS) means operable to establish a DVS control scheme for the master processing module, and DVS liking means operable to relate the DVS control scheme to the slave processing module.
Abstract translation: 计算机装置包括主模块和从模块,使得主模块能够向从模块发送功能请求以供从属模块执行所请求的功能。 主模块包括用于为主处理模块建立DVS控制方案的动态电压缩放(DVS)装置,以及可操作以将DVS控制方案与从属处理模块相关联的DVS喜好装置。
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公开(公告)号:US20080130721A1
公开(公告)日:2008-06-05
申请号:US11946744
申请日:2007-11-28
Applicant: Anthony Craig DOLWIN
Inventor: Anthony Craig DOLWIN
IPC: H04B1/707
CPC classification number: H04B1/7113 , H04B1/709 , H04B1/7115 , H04B1/7117 , H04B2201/70707 , H04B2201/7071 , H04B2201/70711
Abstract: A spread spectrum receiver architecture comprising: a spread spectrum signal sampler; a sample delay stage, coupled to the spread spectrum sampler, to provide a set of spread spectrum samples having a plurality of different delays on a delayed sample bus; a plurality of scramble code generators to provide a plurality of scramble codes on a scramble code bus; and a plurality of correlators, each comprising a correlator module coupled to the delayed sample bus and comprising at least one spreading code generator coupled to the scramble code bus, and each said correlator having at least one correlation output.
Abstract translation: 一种扩频接收机架构,包括:扩频信号采样器; 耦合到扩频采样器的采样延迟级,以在延迟的采样总线上提供具有多个不同延迟的一组扩频样本; 多个扰频码发生器,用于在扰码总线上提供多个扰码; 以及多个相关器,每个相关器包括耦合到所述延迟采样总线的相关器模块,并且包括耦合到所述加扰码总线的至少一个扩展码发生器,并且每个所述相关器具有至少一个相关输出。
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公开(公告)号:US20080209238A1
公开(公告)日:2008-08-28
申请号:US11955846
申请日:2007-12-13
Applicant: Anthony Craig DOLWIN
Inventor: Anthony Craig DOLWIN
IPC: G06F1/00
CPC classification number: G06F1/3203 , G06F1/08 , G06F1/324 , G06F1/329 , G06F1/3296 , Y02D10/126 , Y02D10/172 , Y02D10/24
Abstract: DVS control is established by determining a voltage frequency profile for a processing resource completing a task within a timing deadline. The voltage frequency profile is determined by way of constraining the available operating frequency to a number of discrete permitted operating frequencies. In one embodiment, acceptance of the voltage frequency profile is carried out by determining if the processing resource will carry out a task within an acceptable time period. In one embodiment, this is assessed by reference to a worst case cycle count for the task concerned.
Abstract translation: DVS控制是通过确定在时限期限内完成任务的处理资源的电压频率分布来建立的。 通过将可用的工作频率约束到许多离散的允许的工作频率来确定电压频率分布。 在一个实施例中,通过确定处理资源是否在可接受的时间段内执行任务来执行电压频率分布的接受。 在一个实施例中,这通过参考有关任务的最坏情况周期计数来评估。
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