公开(公告)号：US20190212801A1

公开(公告)日：2019-07-11

申请号：US16249103

申请日：2019-01-16

申请人： Intel Corporation

发明人： Avinash N. Ananthakrishnan ,  Inder M. Sodhi ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Ryan Wells

IPC分类号： G06F1/324 ,  G06F13/40 ,  G06F13/42 ,  G06F1/3293 ,  G06F1/3296 ,  G11C7/22 ,  G06F1/3203

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3293 ,  G06F1/3296 ,  G06F13/4068 ,  G06F13/4282 ,  G11C7/22 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/151

摘要： In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

公开(公告)号：US20190204884A1

公开(公告)日：2019-07-04

申请号：US16294095

申请日：2019-03-06

申请人： International Business Machines Corporation

发明人： Pradip Bose ,  Alper Buyuktosunoglu ,  Timothy Joseph Chainer ,  Pritish Ranjan Parida ,  Augusto Javier Vega

IPC分类号： G06F1/20 ,  G06F1/324 ,  G06F1/3206

CPC分类号： G06F1/206 ,  G06F1/3206 ,  G06F1/324 ,  G06F2200/201 ,  Y02D10/126 ,  Y02D10/16

摘要： Techniques for inducing heterogeneous microprocessor behavior using non-uniform cooling are described. According to an embodiment, a device is provided that comprises an IC chip comprising a plurality of cores and a cooling apparatus coupled to the integrated chip that cools the integrated chip in association with electrical operation of the plurality of cores. The cooling apparatus cools a first core of the plurality of cores to a lower temperature than a second core of the plurality of cores. In various embodiments, the cooling apparatus comprises a plurality of channels embedded within the integrated chip and the cooling apparatus cools the integrated chip via flow of liquid coolant through the plurality of channels.

公开(公告)号：US20180314307A1

公开(公告)日：2018-11-01

申请号：US15966397

申请日：2018-04-30

申请人： Intel Corporation

发明人： Ryan D. Wells ,  Itai Feit ,  Doron Rajwan ,  Nadav Shulman ,  Zeev Offen ,  Inder M. Sodhi

IPC分类号： G06F1/28 ,  G06F1/26 ,  G06F1/32

CPC分类号： G06F1/28 ,  G06F1/266 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126

摘要： In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

公开(公告)号：US20180210530A1

公开(公告)日：2018-07-26

申请号：US15416955

申请日：2017-01-26

申请人： ATI Technologies ULC

发明人： Soon Kyu KWON ,  Jun HUANG ,  Shahriar PEZESHGI ,  Alexander Sabino DUENAS

IPC分类号： G06F1/32 ,  G06T1/20

CPC分类号： G06F1/324 ,  G06F1/3206 ,  G06T1/20 ,  Y02D10/126

摘要： A GPU performs dynamic power level management by switching between pre-defined power levels having distinct clock and voltage levels. The dynamic power level management includes identifying a first performance metric associated with processing workloads at the for a consecutive number of measurement cycles. In some embodiments, the consecutive number of measurement cycles includes a current measurement cycle and at least one previous measurement cycle. Based on a determination that the consecutive number of measurement cycles exceeds a minimum hysteresis number, an estimated optimization is determined to be applied to the GPU for a future measurement cycle. A power level setting at the GPU for the future measurement cycle is adjusted based on the estimated optimization. By considering performance metrics including, for example, different processing workloads and hardware configurations, the GPU is able to dynamically adapt its power settings to the particular workload that it is currently processing.

公开(公告)号：US10013045B2

公开(公告)日：2018-07-03

申请号：US15144332

申请日：2016-05-02

申请人： INTEL CORPORATION

发明人： Stefan Rusu

IPC分类号： G06F1/32 ,  G06F11/30 ,  G06F1/20

CPC分类号： G06F1/324 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/3234 ,  Y02D10/126 ,  Y02D10/16

摘要： Described herein are an apparatus, method, and system for adaptive compensation for reverse temperature dependence in a processor. The apparatus comprises: a first sensor to determine operating temperature of a processor; a second sensor to determine behavior of the processor; and a control unit to determine a frequency of a clock signal for the processor and a power supply level for the processor according to the determined operating temperature and behavior of the processor, wherein the control unit to increase the power supply level from an existing power supply level, and/or reduce frequency of the clock signal from an existing frequency of the clock signal when the operating temperature is in a region of reverse temperature dependence (RTD).

公开(公告)号：US20180181174A1

公开(公告)日：2018-06-28

申请号：US15903702

申请日：2018-02-23

申请人： NetSpeed Systems, Inc.

发明人： Anup GANGWAR ,  Vishunu Mohan Pusuluri ,  Poonacha Kongetira ,  Sailesh Kumar

IPC分类号： G06F1/26

CPC分类号： G06F1/26 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D50/20

摘要： Systems and methods of the present disclosure relate to automatically and/or dynamically generating one or more power management sequences for SoC and NoC architectures from a given input specification having one or a combination of NoC design specification, traffic specification, traffic profile, power profile information, initiator-consumer relationship, interdependency between components, retention information, external factors, among other allied configurations/information to enable efficient switching of one or more hardware elements from one power profile to another.

公开(公告)号：US10007528B2

公开(公告)日：2018-06-26

申请号：US13683748

申请日：2012-11-21

申请人： Intel Corporation

发明人： Guy M. Therien ,  Paul Diefenbaugh ,  Anil Aggarwal ,  Andrew D. Henroid ,  Jeremy J. Shrall ,  Efraim Rotem ,  Krishnakanth V. Sistla ,  Eliezer Weissmann ,  Mohan Kumar ,  Sarathy Jayakumar ,  Jose Andy Vargas ,  Neelam Chandwani ,  Michael A. Rothman ,  Robert Gough ,  Mark Doran

IPC分类号： G06F17/30 ,  G06F9/4401 ,  G06F9/44 ,  G06F9/445 ,  G06F1/28 ,  G06F11/36 ,  G06F1/26 ,  G06F9/22 ,  G06F11/30 ,  G06F11/34 ,  G06F9/30 ,  G06F1/20 ,  G06F15/78 ,  G06F1/32 ,  G06F9/38

CPC分类号： G06F9/4403 ,  G06F1/206 ,  G06F1/26 ,  G06F1/28 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/22 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/384 ,  G06F9/44 ,  G06F9/4401 ,  G06F9/4418 ,  G06F9/445 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3447 ,  G06F11/3466 ,  G06F11/3664 ,  G06F11/3672 ,  G06F11/3688 ,  G06F15/7871 ,  G06F16/2282 ,  G06F2209/501 ,  G06F2217/78 ,  Y02D10/126 ,  Y02D10/172

摘要： In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.

公开(公告)号：US09984038B2

公开(公告)日：2018-05-29

申请号：US15007450

申请日：2016-01-27

申请人： Intel Corporation

发明人： Jose P. Allarey ,  Varghese George ,  Sanjeev S. Jahagirdar ,  Oren Lamdan

IPC分类号： G06F1/00 ,  G06F1/32 ,  G06F15/82 ,  G06F1/20 ,  G06F9/06 ,  G06F15/76 ,  G06F1/08 ,  G06F9/30

CPC分类号： G06F15/82 ,  G06F1/08 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/06 ,  G06F9/30145 ,  G06F15/76 ,  Y02D10/126 ,  Y02D10/16

摘要： With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status.

公开(公告)号：US09983644B2

公开(公告)日：2018-05-29

申请号：US14936945

申请日：2015-11-10

申请人： Intel Corporation

发明人： Shmuel Zobel ,  Maxim Levit ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Dorit Shapira ,  Nadav Shulman

IPC分类号： G06F1/26

CPC分类号： G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： In one embodiment, a processor includes at least one core, at least one thermal sensor, and a power controller including a first logic to dynamically update a time duration for which the at least one core is enabled to be in a turbo mode. Other embodiments are described and claimed.

公开(公告)号：US09983601B2

公开(公告)日：2018-05-29

申请号：US14186932

申请日：2014-02-21

申请人： Rackspace US, Inc.

发明人： Jason Mick ,  Dale Lee Bracey

IPC分类号： G05D23/19 ,  H05K7/14 ,  H05K7/20 ,  G06F11/30 ,  G06F1/32

CPC分类号： G05D23/1917 ,  G05B15/02 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287 ,  G06F9/44505 ,  G06F11/3051 ,  H04L43/08 ,  H04L67/303 ,  H05K7/1492 ,  H05K7/1498 ,  H05K7/20209 ,  H05K7/207 ,  H05K7/20836 ,  Y02D10/126 ,  Y02D10/171

摘要： A rack management method and system is disclosed. The method includes detecting the presence of a computing device releasably mounted in a frame, the detecting based on an electrical connection established between a configuration bar disposed in a rear portion of the frame and the computing device, and determining a physical location of the computing device within the frame based on the electrical connection. The method also includes retrieving management information about the computing device from a profile storage disposed within the computing device via the electrical connection and storing the management information in a management table, the management table associating the computing device with the physical location within the frame.