公开(公告)号：US20250156327A1

公开(公告)日：2025-05-15

申请号：US18506399

申请日：2023-11-10

Applicant: Apollo Autonomous Driving USA LLC

Inventor： ZHENWEI YU

IPC: G06F12/0811 ,  B60W60/00

Abstract: In one embodiment, a system determines a plurality of memory controllers available at a central processing unit (CPU) chipset of an autonomous driving system (ADS) for an autonomous driving vehicle (ADV), the CPU chipset having a plurality of processing cores. The system partitions the plurality of memory controllers at the CPU chipset into N regions. The system determines a shared cache memory at the CPU chipset that is shared among the plurality of processing cores. The system partitions the shared cache memory into N segments according to the N regions. The system configures CPU chipset settings to associate each memory controller in the N regions to a segment of the shared cache memory in the respective region. Data and/or instruction sets are accessed by the CPU chipset from a memory controller through a segment of the cache memory that is associated to the memory controller.