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公开(公告)号：US20230075465A1
公开(公告)日：2023-03-09
申请号：US17468482
申请日：2021-09-07
Applicant: Apple Inc.
Inventor： Andreas Menkhoff , Andreas Boehme , Bernhard Sogl , Jochen Schrattenecker , Joonhoi Hur
Abstract: An electronic device may include wireless circuitry. The wireless circuitry may include a quadratic phase generator for outputting a perfectly interpolated constant amplitude zero autocorrelation (CAZAC) sequence for a transmit path. The quadratic phase generator may include a numerically controlled oscillator, a switch controlled based on a value output from the numerically controlled oscillator, a first integrator stage, and a second integrator stage connected in series with the first integrator stage. The numerically controlled oscillator may receive as inputs a chirp count and a word length. The switch may be configured to switchably feed one of two input values that are a function of the chirp count and the word length to the first integrator stage. The quadratic phase generator may output full-bandwidth chirps or reduced-bandwidth chirps. Bandwidth reduction can be achieved by scaling the two input values of the switches.
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公开(公告)号：US20230291432A1
公开(公告)日：2023-09-14
申请号：US18319664
申请日：2023-05-18
Applicant: Apple Inc.
Inventor： Andreas Menkhoff , Andreas Boehme , Bernhard Sogl , Jochen Schrattenecker , Joonhoi Hur
CPC classification number: H04B1/40 , H03K5/01 , H03K2005/00013
Abstract: An electronic device may include wireless circuitry. The wireless circuitry may include a quadratic phase generator for outputting a perfectly interpolated constant amplitude zero autocorrelation (CAZAC) sequence for a transmit path. The quadratic phase generator may include a numerically controlled oscillator, a switch controlled based on a value output from the numerically controlled oscillator, a first integrator stage, and a second integrator stage connected in series with the first integrator stage. The numerically controlled oscillator may receive as inputs a chirp count and a word length. The switch may be configured to switchably feed one of two input values that are a function of the chirp count and the word length to the first integrator stage. The quadratic phase generator may output full-bandwidth chirps or reduced-bandwidth chirps. Bandwidth reduction can be achieved by scaling the two input values of the switches.
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公开(公告)号：US12052047B2
公开(公告)日：2024-07-30
申请号：US18319664
申请日：2023-05-18
Applicant: Apple Inc.
Inventor： Andreas Menkhoff , Andreas Boehme , Bernhard Sogl , Jochen Schrattenecker , Joonhoi Hur
CPC classification number: H04B1/40 , H03K5/01 , H03K2005/00013
Abstract: An electronic device may include wireless circuitry. The wireless circuitry may include a quadratic phase generator for outputting a perfectly interpolated constant amplitude zero autocorrelation (CAZAC) sequence for a transmit path. The quadratic phase generator may include a numerically controlled oscillator, a switch controlled based on a value output from the numerically controlled oscillator, a first integrator stage, and a second integrator stage connected in series with the first integrator stage. The numerically controlled oscillator may receive as inputs a chirp count and a word length. The switch may be configured to switchably feed one of two input values that are a function of the chirp count and the word length to the first integrator stage. The quadratic phase generator may output full-bandwidth chirps or reduced-bandwidth chirps. Bandwidth reduction can be achieved by scaling the two input values of the switches.
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公开(公告)号：US11863225B2
公开(公告)日：2024-01-02
申请号：US17468482
申请日：2021-09-07
Applicant: Apple Inc.
Inventor： Andreas Menkhoff , Andreas Boehme , Bernhard Sogl , Jochen Schrattenecker , Joonhoi Hur
CPC classification number: H04B1/40 , H03K5/01 , H03K2005/00013
Abstract: An electronic device may include wireless circuitry. The wireless circuitry may include a quadratic phase generator for outputting a perfectly interpolated constant amplitude zero autocorrelation (CAZAC) sequence for a transmit path. The quadratic phase generator may include a numerically controlled oscillator, a switch controlled based on a value output from the numerically controlled oscillator, a first integrator stage, and a second integrator stage connected in series with the first integrator stage. The numerically controlled oscillator may receive as inputs a chirp count and a word length. The switch may be configured to switchably feed one of two input values that are a function of the chirp count and the word length to the first integrator stage. The quadratic phase generator may output full-bandwidth chirps or reduced-bandwidth chirps. Bandwidth reduction can be achieved by scaling the two input values of the switches.
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