Method for multiplexing between power supply signals for voltage limited circuits

    公开(公告)号:US10084450B1

    公开(公告)日:2018-09-25

    申请号:US15671524

    申请日:2017-08-08

    申请人: Apple Inc.

    摘要: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.

    AN ELECTRIC FENCE ENERGISER SYSTEM AND METHODS OF OPERATION AND COMPONENTS THEREOF

    公开(公告)号:US20170303375A1

    公开(公告)日:2017-10-19

    申请号:US15510367

    申请日:2015-09-11

    申请人: TRU-TEST LIMITED

    IPC分类号: H05C1/04 H03K3/02 H01F30/02

    摘要: An electric fence energizer including an IPC (isolated power coupling) power transmitter and an IPC power receiver adapted to receive power from the IPC power transmitter and supply power to the energizer. A pulse shaping circuit between an energy source and output transformer of the energizer may include a series inductance of between 2 μH to 20 μH and a parallel capacitance of between 3μF to 30 μF. The energizer output transformer may comprise a primary winding consisting of less than 15 turns and a secondary winding of between 5 and 50 times the number of turns of the primary winding. The energizer may produce a pulse having a duration of between 20 μs and 60 μs and a peak amplitude greater than 5 kV into 300 Ω.

    DATA SERIALIZATION CIRCUIT
    8.
    发明申请

    公开(公告)号:US20170279461A1

    公开(公告)日:2017-09-28

    申请号:US15409478

    申请日:2017-01-18

    IPC分类号: H03M9/00 H03K3/037 H03K5/01

    摘要: The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.