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1.
公开(公告)号:US20180331862A1
公开(公告)日:2018-11-15
申请号:US16041129
申请日:2018-07-20
发明人: Shwetabh VERMA , Bhaskar Banerjee , Amiad DVIR , Assaf NAOR
IPC分类号: H04L25/03
CPC分类号: H04L25/03834 , H03H7/06 , H03K5/01 , H03K5/24 , H03K2005/00058
摘要: Methods, systems, and apparatuses are described for improving the signal integrity of a differential pair of signals by mitigating a non-balanced channel deficiency. For example, signal integrity may be improved by independently shaping and/or independently controlling the slopes (e.g., the rising edge and/or falling edge) of each signal of a differential pair of signals to counteract the effects caused by non-balanced deficiencies to provide a balanced differential pair of signals (i.e., signals having symmetrical impedances, loads, etc.).
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公开(公告)号:US10084450B1
公开(公告)日:2018-09-25
申请号:US15671524
申请日:2017-08-08
申请人: Apple Inc.
发明人: Keith Cox , Victor Zyuban , Norman J Rohrer
IPC分类号: G11C5/04 , H03K19/0175 , H03K5/01 , H03K5/00
CPC分类号: H03K19/017509 , G11C5/147 , H02J2001/008 , H03K5/01 , H03K2005/00013
摘要: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.
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公开(公告)号:US20180219537A1
公开(公告)日:2018-08-02
申请号:US15704641
申请日:2017-09-14
申请人: SK hynix Inc.
发明人: Jeong-Eun SONG
摘要: An electronic device may include a ramp signal generator suitable for generating a ramp signal having a slope corresponding to an analog gain, and a slope correction circuit suitable for correcting the slope based on a correction code signal.
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公开(公告)号:US20180095493A1
公开(公告)日:2018-04-05
申请号:US15722249
申请日:2017-10-02
申请人: ROHM Co., LTD.
发明人: Makoto YASUSAKA
CPC分类号: G06F1/04 , G06F1/26 , G06F1/3203 , G06F1/3234 , H02M1/36 , H03K3/012 , H03K3/037 , H03K5/01 , H03K5/08 , H03L7/24
摘要: Disclosed herein is an enable signal generation circuit. The circuit includes: an enable input terminal that receives an enable input voltage; an enable detection circuit that determines whether the enable input voltage is higher than a first reference voltage, and then outputs an inverted signal; and an output section that is connected to the enable detection circuit. The enable detection circuit is formed of at least two transistors arranged in a differential configuration, gives the two transistors offset voltages that provide different operating voltages, and causes the output section to output a signal based on the inverted signal.
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公开(公告)号:US20180054191A1
公开(公告)日:2018-02-22
申请号:US15800848
申请日:2017-11-01
申请人: Inphi Corporation
CPC分类号: H03K5/023 , H03F3/3001 , H03F3/3033 , H03F3/45076 , H03F3/45179 , H03F3/68 , H03G3/20 , H03K3/012 , H03K5/01 , H03K5/02 , H03M1/1245 , H03M1/38 , H03M1/66 , H04B1/16
摘要: The present disclosure provides a detailed description of techniques for implementing a low power buffer with dynamic gain control. More specifically, some embodiments of the present disclosure are directed to a buffer having a gain boost configuration and a current shunt circuit to control the gain of a respective gain boosting transistor of the gain boost configuration. The current shunt circuit and resulting gain are dynamically controlled by a gain control signal such that the buffer gain can be adjusted to within an acceptable range of the target gain for the current operating and device mismatch conditions. In one or more embodiments, the gain boost configuration with dynamic gain control can be deployed in a full differential implementation. Both analog and digital dynamic calibration and control techniques can be used to provide the gain control signals to multiple current shunt circuits and multiple buffers.
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6.
公开(公告)号:US09825616B2
公开(公告)日:2017-11-21
申请号:US14928830
申请日:2015-10-30
IPC分类号: H03F1/14 , H03K5/01 , H03K17/60 , H03F3/19 , H03G3/30 , H03F1/02 , H03F3/21 , H03K6/04 , H03G3/00
CPC分类号: H03K5/01 , H03F1/0255 , H03F3/19 , H03F3/21 , H03F2200/102 , H03F2200/451 , H03G3/007 , H03G3/3042 , H03K6/04 , H03K17/60
摘要: A wave shaping circuit reduces slope magnitudes during increasing and decreasing voltage transitions. The wave shaping circuit includes a first switch that receives an input voltage having at least two voltage values where an input voltage transition between the at least two voltage values has a first slope magnitude; an inductor connected in series with the first switch; a second switch connected in a parallel arrangement with the first switch and the inductor; and a capacitor having a first end connected between the inductor and an output port and a second end connected to ground. When the input voltage begins the input voltage transition to a higher voltage value, the first switch turns on and the second switch turns off, such that the inductor limits current flow from the input voltage, decreasing a second slope magnitude of an output voltage transition to less than the first slope magnitude.
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公开(公告)号:US20170303375A1
公开(公告)日:2017-10-19
申请号:US15510367
申请日:2015-09-11
申请人: TRU-TEST LIMITED
摘要: An electric fence energizer including an IPC (isolated power coupling) power transmitter and an IPC power receiver adapted to receive power from the IPC power transmitter and supply power to the energizer. A pulse shaping circuit between an energy source and output transformer of the energizer may include a series inductance of between 2 μH to 20 μH and a parallel capacitance of between 3μF to 30 μF. The energizer output transformer may comprise a primary winding consisting of less than 15 turns and a secondary winding of between 5 and 50 times the number of turns of the primary winding. The energizer may produce a pulse having a duration of between 20 μs and 60 μs and a peak amplitude greater than 5 kV into 300 Ω.
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公开(公告)号:US20170279461A1
公开(公告)日:2017-09-28
申请号:US15409478
申请日:2017-01-18
发明人: Shih-Chun Lin , Ren-Hong Luo , Mu-Jung Chen , Yung-Cheng Lin
CPC分类号: H03M9/00 , H03K3/037 , H03K5/01 , H03K5/15046 , H03K2005/00019
摘要: The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.
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公开(公告)号:US20170250696A1
公开(公告)日:2017-08-31
申请号:US15223057
申请日:2016-07-29
申请人: SK hynix Inc.
发明人: Ha Jun JEONG
CPC分类号: H03L7/24 , G06F1/04 , H03K5/01 , H03K5/1534 , H03K2005/00019
摘要: A signal recovery circuit includes a clock code generation circuit configured to generate codes in response to an enable signal and a clock, and a pulse recovery circuit configured to generate an output pulse in response to an input pulse and the codes.
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公开(公告)号:US20170155381A1
公开(公告)日:2017-06-01
申请号:US15431374
申请日:2017-02-13
发明人: Marco Raimondi , Edoardo Botti
IPC分类号: H03K5/1252 , H03K4/08 , H03K7/08
摘要: A method is for reducing pulse skipping from a characteristic affecting a modulating signal input to an integrator of a pulse width modulation (PWM) modulator, together with a square wave carrier signal for generating a triangular waveform of the PWM modulator. The method may include creating a broad synchronous peak at vertexes of the triangular waveform output by the integrator.
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