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公开(公告)号：US20250095274A1
公开(公告)日：2025-03-20
申请号：US18524265
申请日：2023-11-30
Applicant: Apple Inc.
Inventor： Ali Rabbani Rankouhi , Luca O. Iuliano , David J. Bermingham , Christopher A. Burns
Abstract: Techniques are disclosed relating to graphics processors that support ray tracing. In disclosed embodiments, ray intersect circuitry is configured to access a traversal stack used for traversal of multiple levels of a bounding volume hierarchy (BVH) acceleration data structure (ADS) according to a depth-first search to retrieve: coordinates of a first bounding region for a child node and a local ray parameter value that indicates a point along a ray at which an intersection with a second bounding region for the child node's parent node was detected. The accelerator circuitry may compare the local ray parameter value with an end ray parameter value to determine whether to traverse to the child node as part of traversal of the BVH.
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公开(公告)号：US20250095272A1
公开(公告)日：2025-03-20
申请号：US18405191
申请日：2024-01-05
Applicant: Apple Inc.
Inventor： Ali Rabbani Rankouhi , David J. Bermingham
Abstract: Techniques are disclosed relating to ray tracing, e.g., in graphics processors. Ray tracing embodiments may utilize a bounding volume hierarchy (BVH) acceleration data structure (ADS) that includes a hierarchy of bounding volumes. A graphics processor may traverse the ADS, testing for intersections with bounding volumes, to determine which primitives to test for a given ray. Some nodes may be transform nodes (e.g., instance nodes) that correspond to a ray transform before further traversal. In disclosed embodiment, one or more levels below the transform node may be reverse transformed and included above the transform node. This may advantageously avoid a ray transform operation for rays that would not have hit in the first one or more levels of the transform sub-tree.
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公开(公告)号：US20250095264A1
公开(公告)日：2025-03-20
申请号：US18391260
申请日：2023-12-20
Applicant: Apple Inc.
Inventor： Ali Rabbani Rankouhi , David J. Bermingham , Fergus W. MacGarry
Abstract: Techniques are disclosed relating to caching data for ray tracing in graphics processors. In some embodiments, ray intersect accelerator circuitry includes traversal circuitry configured to perform intersection tests between rays and bounding regions of an acceleration data structure and transform circuitry configured to, in response to reaching a transform node in the acceleration data structure, transform first coordinates of a ray from a first coordinate space to generate second coordinates of the ray in a second coordinate space. Ray cache circuitry is configured to cache data that is accessible to the ray intersect accelerator circuitry, where an entry of the ray cache circuitry is configured to cache data for the ray that includes: the first coordinates of the ray in the first coordinate space, the second coordinates of the ray in the second coordinate space, and shared data for the ray that applies to both the first and second coordinates.
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