公开(公告)号：US11474795B2

公开(公告)日：2022-10-18

申请号：US16128459

申请日：2018-09-11

Applicant: Apple Inc.

Inventor： Nader W. Moussa ,  Etienne Belanger

IPC: G06F8/41

Abstract: Embodiments described herein provide for a non-transitory machine-readable medium storing instructions to cause one or more processors to perform operations processing, in an integrated development environment, a set of program code to identify an assertion within the set of program code; determining compile-time provability of a condition specified by the assertion; and presenting an error condition in response to failing to determine compile-time provability of the condition specified by the assertion, wherein determining compile-time provability of the condition specified by the assertion includes semantically converting the condition specified by the assertion into a Boolean, reducing the Boolean to an intermediate representation, and processing the intermediate representation to detect an expression within the intermediate representation that is non-constant at compile-time.

公开(公告)号：US12020168B2

公开(公告)日：2024-06-25

申请号：US16262807

申请日：2019-01-30

Applicant: Apple Inc.

Inventor： Francesco Rossi ,  Cecile M. Foret ,  Gaurav Kapoor ,  Kit-Man Wan ,  Umesh S. Vaishampayan ,  Etienne Belanger

IPC: G06N3/10 ,  G06F9/46 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06N3/10 ,  G06F9/461 ,  G06F9/4881 ,  G06F9/5038

Abstract: The subject technology runs a compiled neural network (NN) model on a particular processor with multiple priority queues for executing different processes, the compiled NN model being assigned to a particular priority queue, and the compiled NN model includes context switch instructions that were previously inserted into a neural network (NN) model from which the compiled NN model was compiled. The subject technology determines that a particular context switch instruction has been executed by the particular processor. The subject technology determines that a different process is waiting to be executed, the different process being assigned to a different priority queue and the different process being a higher priority process than the running compiled NN model. In response to executing the particular context switch instruction, the subject technology performs a context switch to the different process assigned to the different priority queue when the different process is waiting to be executed.

公开(公告)号：US12175375B2

公开(公告)日：2024-12-24

申请号：US17903991

申请日：2022-09-06

Applicant: Apple Inc.

Inventor： Gaurav Kapoor ,  Cecile M. Foret ,  Francesco Rossi ,  Kit-Man Wan ,  Umesh S. Vaishampayan ,  Etienne Belanger ,  Albert Antony ,  Alexey Marinichev ,  Marco Zuliani ,  Xiaojin Shi

IPC: G06N3/10 ,  G06F8/41 ,  G06F9/50 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: The subject technology provides receiving a neural network (NN) model to be executed on a target platform, the NN model including multiple layers that include operations and some of the operations being executable on multiple processors of the target platform. The subject technology further sorts the operations from the multiple layers in a particular order based at least in part on grouping the operations that are executable by a particular processor of the multiple processors. The subject technology determines, based at least in part on a cost of transferring the operations between the multiple processors, an assignment of one of the multiple processors for each of the sorted operations of each of the layers in a manner that minimizes a total cost of executing the operations. Further, for each layer of the NN model, the subject technology includes an annotation to indicate the processor assigned for each of the operations.

公开(公告)号：US12051006B2

公开(公告)日：2024-07-30

申请号：US17903991

申请日：2022-09-06

Applicant: Apple Inc.

Inventor： Gaurav Kapoor ,  Cecile M. Foret ,  Francesco Rossi ,  Kit-Man Wan ,  Umesh S. Vaishampayan ,  Etienne Belanger ,  Albert Antony ,  Alexey Marinichev ,  Marco Zuliani ,  Xiaojin Shi

IPC: G06N3/10 ,  G06F8/41 ,  G06F9/50 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

CPC classification number: G06N3/10 ,  G06F8/41 ,  G06F8/443 ,  G06F8/4441 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06F9/50 ,  G06N3/08 ,  G06N3/063 ,  G06N3/04 ,  G06N3/10

Abstract: The subject technology provides receiving a neural network (NN) model to be executed on a target platform, the NN model including multiple layers that include operations and some of the operations being executable on multiple processors of the target platform. The subject technology further sorts the operations from the multiple layers in a particular order based at least in part on grouping the operations that are executable by a particular processor of the multiple processors. The subject technology determines, based at least in part on a cost of transferring the operations between the multiple processors, an assignment of one of the multiple processors for each of the sorted operations of each of the layers in a manner that minimizes a total cost of executing the operations. Further, for each layer of the NN model, the subject technology includes an annotation to indicate the processor assigned for each of the operations.

公开(公告)号：US11468338B2

公开(公告)日：2022-10-11

申请号：US16262809

申请日：2019-01-30

Applicant: Apple Inc.

Inventor： Francesco Rossi ,  Cecile M. Foret ,  Gaurav Kapoor ,  Kit-Man Wan ,  Umesh S. Vaishampayan ,  Etienne Belanger ,  Albert Antony ,  Alexey Marinichev ,  Marco Zuliani ,  Xiaojin Shi

IPC: G06N3/10 ,  G06N3/08 ,  G06N3/04 ,  G06F8/41 ,  G06N3/063 ,  G06F9/50

Abstract: The subject technology provides receiving a neural network (NN) model to be executed on a target platform, the NN model including multiple layers that include operations and some of the operations being executable on multiple processors of the target platform. The subject technology further sorts the operations from the multiple layers in a particular order based at least in part on grouping the operations that are executable by a particular processor of the multiple processors. The subject technology determines, based at least in part on a cost of transferring the operations between the multiple processors, an assignment of one of the multiple processors for each of the sorted operations of each of the layers in a manner that minimizes a total cost of executing the operations. Further, for each layer of the NN model, the subject technology includes an annotation to indicate the processor assigned for each of the operations.

公开(公告)号：US20200081693A1

公开(公告)日：2020-03-12

申请号：US16128459

申请日：2018-09-11

Applicant: Apple Inc.

Inventor： Nader W. Moussa ,  Etienne Belanger

IPC: G06F8/41

Abstract: Embodiments described herein provide for a non-transitory machine-readable medium storing instructions to cause one or more processors to perform operations processing, in an integrated development environment, a set of program code to identify an assertion within the set of program code; determining compile-time provability of a condition specified by the assertion; and presenting an error condition in response to failing to determine compile-time provability of the condition specified by the assertion, wherein determining compile-time provability of the condition specified by the assertion includes semantically converting the condition specified by the assertion into a Boolean, reducing the Boolean to an intermediate representation, and processing the intermediate representation to detect an expression within the intermediate representation that is non-constant at compile time