公开(公告)号：US20190205756A1

公开(公告)日：2019-07-04

申请号：US16297091

申请日：2019-03-08

申请人： Google LLC

发明人： Olivier Temam ,  Harshit Khaitan ,  Ravi Narayanaswami ,  Dong Hyuk Woo

IPC分类号： G06N3/08 ,  G06N20/00 ,  G06F8/41 ,  G06N3/063

CPC分类号： G06N3/08 ,  G06F8/4441 ,  G06F8/452 ,  G06F9/50 ,  G06N3/04 ,  G06N3/063 ,  G06N20/00 ,  G06T1/20

摘要： Methods, systems, and apparatus for accessing a N-dimensional tensor are described. In some implementations, a method includes, for each of one or more first iterations of a first nested loop, performing iterations of a second nested loop that is nested within the first nested loop until a first loop bound for the second nested loop is reached. A number of iterations of the second nested loop for the one or more first iterations of the first nested loop is limited by the first loop bound in response to the second nested loop having a total number of iterations that exceeds a value of a hardware property of the computing system. After a penultimate iteration of the first nested loop has completed, one or more iterations of the second nested loop are performed for a final iteration of the first nested loop until an alternative loop bound is reached.

公开(公告)号：US20190197015A1

公开(公告)日：2019-06-27

申请号：US16042803

申请日：2018-07-23

申请人： Hyperion Core, Inc.

发明人： Martin Vorbach

IPC分类号： G06F15/78 ,  G06F9/30 ,  G06F9/345 ,  G06F9/38

CPC分类号： G06F15/7839 ,  G06F8/4441 ,  G06F8/452 ,  G06F9/30043 ,  G06F9/3017 ,  G06F9/345 ,  G06F9/38 ,  G06F15/7821 ,  G06F2213/0038 ,  G11C8/16 ,  G11C11/412 ,  Y02D10/12 ,  Y02D10/13

摘要： The invention relates to a multi-core processor memory system, wherein it is provided that the system comprises memory channels between the multi-core processor and the system memory, and that the system comprises at least as many memory channels as processor cores, each memory channel being dedicated to a processor core, and that the memory system relates at run-time dynamically memory blocks dedicatedly to the accessing core, the accessing core having dedicated access to the memory bank via the memory channel.

公开(公告)号：US20190188113A1

公开(公告)日：2019-06-20

申请号：US16285781

申请日：2019-02-26

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Takuya Nakaike ,  Takeshi Ogasawara

IPC分类号： G06F11/36 ,  G06F8/41

CPC分类号： G06F11/3608 ,  G06F8/4441 ,  G06F8/45 ,  G06F8/458 ,  G06F11/3612 ,  G06F11/3644 ,  G06F11/3664

摘要： Described is a computer-implemented method of reordering condition checks. Two or more condition checks in computer code that may be reordered within the code are identified. It is determined that the execution frequency of a later one of the condition checks is satisfied at a greater frequency than a preceding one of the condition checks. It is determined that there is an absence of side effects in the two or more condition checks. The values of the condition checks are propagated and abstract interpretation is performed on the values that are propagated. It is determined that the condition checks are exclusive of each other, and the condition checks are reordered within the computer code.

公开(公告)号：US20190042217A1

公开(公告)日：2019-02-07

申请号：US15855964

申请日：2017-12-27

申请人： Intel Corporation

发明人： Kent Glossop ,  Kermin Fleming ,  Yongzhi Zhang ,  Simon Steely, JR. ,  James Sukha ,  Uma Srinivasan

IPC分类号： G06F8/41

CPC分类号： G06F8/433 ,  G06F8/441 ,  G06F8/443 ,  G06F8/4441 ,  G06F8/447

摘要： Methods, apparatus, systems and articles of manufacture to compiler compile code to generate dataflow code are described. An example compiler apparatus includes an intermediate representation transformer to transform input software code to intermediate representation code; an instruction selector to insert machine instructions of a target execution platform in the intermediate representation code to generate machine intermediate representation code; and a target machine transformer to: convert a portion of the machine intermediate representation code to dataflow code to generate dataflow intermediate representation code; and allocate registers within the dataflow intermediate representation code.

公开(公告)号：US20180373515A1

公开(公告)日：2018-12-27

申请号：US15632286

申请日：2017-06-23

申请人： MICROSOFT TECHNOLOGY LICENSING, LLC.

发明人： MORGAN ASHER BROWN ,  DAVID CHARLES WRIGHTON ,  MEI-CHIN TSAI ,  SHAH MOHAMMAD FAIZUR RAHMAN ,  YI ZHANG ,  IAN M. BEARMAN ,  ERDEMBILEGT JANCHIVDORJ ,  DAVID ADAM HARTGLASS ,  DAVID MITFORD GILLIES

IPC分类号： G06F9/45

CPC分类号： G06F8/4441 ,  G06F8/433 ,  G06F8/4434 ,  G06F8/4443 ,  G06F8/447 ,  G06F9/4552

摘要： A mechanism for generating optimized native code for a program having dynamic behavior uses a static analysis of the program to predict the likelihood that different elements of the program are likely to be used when the program executes. The static analysis is performed prior to execution of the program and marks certain elements of the program with confidence indicators that classify the elements with either a high level of confidence or a low level of confidence. The confidence indicators are then used by an ahead-of-time native compiler to generate native code and to optimize the code for faster execution and/or a smaller-sized native code.

公开(公告)号：US20180365561A1

公开(公告)日：2018-12-20

申请号：US15627022

申请日：2017-06-19

申请人： Google Inc.

发明人： Olivier Temam ,  Harshit Khaitan ,  Ravi Narayanaswami ,  Dong Hyuk Woo

IPC分类号： G06N3/08 ,  G06N99/00

CPC分类号： G06N3/08 ,  G06F8/4441 ,  G06F8/452 ,  G06F9/50 ,  G06N99/005 ,  G06T1/20

摘要： Methods, systems, and apparatus for accessing a N-dimensional tensor are described. In some implementations, a method includes, for each of one or more first iterations of a first nested loop, performing iterations of a second nested loop that is nested within the first nested loop until a first loop bound for the second nested loop is reached. A number of iterations of the second nested loop for the one or more first iterations of the first nested loop is limited by the first loop bound in response to the second nested loop having a total number of iterations that exceeds a value of a hardware property of the computing system. After a penultimate iteration of the first nested loop has completed, one or more iterations of the second nested loop are performed for a final iteration of the first nested loop until an alternative loop bound is reached.

公开(公告)号：US20180314945A1

公开(公告)日：2018-11-01

申请号：US15498943

申请日：2017-04-27

申请人： Advanced Micro Devices, Inc.

发明人： Mauricio Breternitz ,  Mayank Daga

IPC分类号： G06N3/08 ,  G06N3/04

CPC分类号： G06F1/3243 ,  G06F8/4436 ,  G06F8/4441 ,  G06F8/447 ,  G06N3/0454 ,  G06N3/063 ,  G06N5/022

摘要： Systems, apparatuses, and methods for enhanced resolution video and security via machine learning are disclosed. A system is configured to receive a source code representation of a neural network. In one embodiment, the source code representation is a directed acyclic graph (DAG). The system determines if the source code representation includes any of one or more patterns, with each pattern including two or more adjacent layers. The system also identifies, for each pattern, a combined layer with which to replace the detected pattern. If any occurrences of the one or more patterns are detected in the source code representation, the system replaces each pattern with a corresponding combined layer. Additionally, the system generates an optimized representation of the neural network, wherein the optimized representation includes replacements for any detected patterns. The optimized representation can be utilized to generate an executable version of the neural network.

公开(公告)号：US10061582B2

公开(公告)日：2018-08-28

申请号：US14143926

申请日：2013-12-30

申请人： Intellectual Ventures Holding 81 LLC

发明人： Richard Johnson ,  Guillermo Rozas

IPC分类号： G06F9/44 ,  G06F9/30 ,  G06F8/41

CPC分类号： G06F9/30065 ,  G06F8/4441

摘要： A method for increasing the speed of execution by a processor including the steps of selecting a sequence of instructions to optimize, optimizing the sequence of instructions, creating a duplicate of instructions from the sequence of instructions which has been selected to optimize, executing the optimized sequence of instructions, and responding to an error during the execution of the optimized sequence of instructions by rolling back to the duplicate of instructions from the sequence of instructions.

公开(公告)号：US10061571B2

公开(公告)日：2018-08-28

申请号：US15273511

申请日：2016-09-22

申请人： Qualcomm Innovation Center, Inc.

发明人： Sergei Larin ,  Shankar Kalpathi Easwaran ,  Hemant Kulkarni

IPC分类号： G06F8/41 ,  G06F8/54 ,  G06F9/445

CPC分类号： G06F8/4441 ,  G06F8/41 ,  G06F8/427 ,  G06F8/443 ,  G06F8/4435 ,  G06F8/54 ,  G06F9/44521

摘要： A method for link time optimization comprises parsing, by a compiler, an intermediate representation file to determine what symbols are present in the intermediate representation file. The method comprises providing the symbols to a linker and creating, by the linker, a symbol use tree of all the symbols that are present in the intermediate representation file and other symbols in binary code received by the linker. The method further comprises discarding, by the linker, any received objects for which no use can be identified and all dependencies of the objects. The method includes providing, from the linker to the compiler, a preserve list of symbols, the preserve list comprising a list of symbols proven used by the objects and the intermediate representation files. The method comprises compiling the intermediate representation files and the objects based on the preserve list of symbols, and deleting, by the linker, any remaining unused objects.

公开(公告)号：US20180225101A1

公开(公告)日：2018-08-09

申请号：US15943188

申请日：2018-04-02

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Michael K. Gschwind ,  Ronald I. McIntosh

IPC分类号： G06F8/41 ,  G06F11/36 ,  G06F9/30 ,  G06F7/76 ,  G06F13/40

CPC分类号： G06F8/443 ,  G06F7/76 ,  G06F7/768 ,  G06F8/41 ,  G06F8/4441 ,  G06F9/30036 ,  G06F11/3624 ,  G06F13/4013

摘要： An application that includes intrinsics defined in one architecture is to execute without change on a different architecture. Program code that depends on vector element ordering is obtained, and that program code is part of an application including one or more intrinsics. The one or more intrinsics are mapped from a first system architecture for which the application was written to a second system architecture. One or more operations of the program code are then converted from a first data layout to a second data layout. The application, including the mapped intrinsics and the converted data layout, is to be executed on a processor of the different architecture.