公开(公告)号：US09564582B2

公开(公告)日：2017-02-07

申请号：US14201439

申请日：2014-03-07

Applicant: Applied Materials, Inc.

Inventor： Mahendra Pakala ,  Mihaela Balseanu ,  Jonathan Germain ,  Jaesoo Ahn ,  Lin Xue

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L27/222 ,  H01L43/08

Abstract: A method for fabricating an MRAM bit that includes depositing a spacer layer that protects the tunneling barrier layer during processing is disclosed. The deposited spacer layer prevents byproducts formed in later processing from redepositing on the tunneling barrier layer. Such redeposition may lead to product failure and decreased manufacturing yield. The method further includes non-corrosive processing conditions that prevent damage to the layers of MRAM bits. The non-corrosive processing conditions may include etching without using a halogen-based plasma. Embodiments disclosed herein use an etch-deposition-etch sequence that simplifies processing.

Abstract translation: 公开了一种用于制造MRAM位的方法，其包括在处理期间沉积保护隧道势垒层的间隔层。 沉积的间隔层防止在后续处理中形成的副产物再沉积在隧道势垒层上。 这种再沉积可能导致产品失效并降低了制造成品率。 该方法还包括防腐损坏处理条件，以防损坏MRAM位的层。 非腐蚀性处理条件可以包括不使用卤素等离子体的蚀刻。 本文公开的实施例使用简化处理的蚀刻 - 沉积蚀刻序列。

公开(公告)号：US20140308758A1

公开(公告)日：2014-10-16

申请号：US13934017

申请日：2013-07-02

Applicant: Applied Materials, Inc.

Inventor： Srinivas D. Nemani ,  Sumit Agarwal ,  Jeremiah T. Pender ,  Jonathan Germain ,  Khoi Doan ,  Bradley Howard

IPC: H01L43/12

CPC classification number: H01L43/12

Abstract: Methods of forming material junctions for magnetic memory devices are described. The methods involve providing a material stack including a bottom magnetic tunneling junction layer, a tunneling barrier layer, and a top magnetic tunneling junction layer (from bottom to top) on a substrate. The top magnetic tunneling junction layer is patterned to form a top magnetic tunneling junction and then a dielectric spacer layer may be formed over the top magnetic tunneling junction. The dielectric spacer is etched to leave a vertical dielectric spacer to maintain electrical separation between the top magnetic tunneling junction and the bottom magnetic tunneling junction during and following subsequent etching/processing. In an alternative embodiment the spacer layer is lithographically defined.

Abstract translation: 描述了形成用于磁存储器件的材料结的方法。 所述方法包括在衬底上提供包括底部磁隧道结层，隧道势垒层和顶部磁性隧道结层（从底部到顶部）的材料堆叠。 将顶部磁隧道结层图案化以形成顶部磁性隧道结，然后可以在顶部磁性隧道结上方形成电介质间隔层。 蚀刻电介质间隔物以留下垂直电介质间隔物，以在随后的蚀刻/处理期间和之后保持顶部磁隧道结与底部磁性隧道结之间的电分离。 在替代实施例中，间隔层被光刻地限定。