公开(公告)号：US20210011638A1

公开(公告)日：2021-01-14

申请号：US16507348

申请日：2019-07-10

Applicant: Arm Limited

Inventor： Christopher Neal HINDS ,  Jesse Garrett BEU ,  Alejandro RICO CARRO ,  Jose Alberto JOAO

IPC: G06F3/06 ,  G06F9/30

Abstract: Non-volatile storage circuitry is provided as primary storage accessible to processing circuitry, e.g. as registers, a cache, scratchpad memory, TLB or on-chip RAM. Power control circuitry powers down a given region of the non-volatile storage circuitry when information stored in said given region is not being used. This provides opportunities for more frequent power savings than would be possible if primary storage was implemented using volatile storage.

公开(公告)号：US20220382703A1

公开(公告)日：2022-12-01

申请号：US17335378

申请日：2021-06-01

Applicant: Arm Limited

Inventor： Timothy HAYES ,  Alejandro RICO CARRO ,  Tushar P. RINGE ,  Kishore Kumar JAGADEESHA

IPC: G06F13/40 ,  G06F12/0875

Abstract: An apparatus comprises an interconnect providing communication paths between agents coupled to the interconnect. A coordination agent is provided which performs an operation requiring sending a request to each of a plurality of target agents, and receiving a response from each of the target agents, the operation being unable to complete until the response has been received from each of the target agents. Storage circuitry is provided which is accessible to the coordination agent and configured to store, for each agent that the coordination agent may communicate with via the interconnect, a latency indication for communication between that agent and the coordination agent. The coordination agent is configured, prior to performing the operation, to determine a sending order in which to send the request to each of the target agents, the sending order being determined in dependence on the latency indication for each of the target agents.

公开(公告)号：US20220413866A1

公开(公告)日：2022-12-29

申请号：US17355641

申请日：2021-06-23

Applicant: Arm Limited

Inventor： Krishnendra NATHELLA ,  David Hennah MANSELL ,  Alejandro RICO CARRO ,  Andrew MUNDY

IPC: G06F9/38 ,  G06F12/12

Abstract: In response to an instruction decoder decoding a range prefetch instruction specifying first and second address-range-specifying parameters and a stride parameter, prefetch circuitry controls, depending on the first and second address-range-specifying parameters and the stride parameter, prefetching of data from a plurality of specified ranges of addresses into the at least one cache. A start address and size of each specified range is dependent on the first and second address-range-specifying parameters. The stride parameter specifies an offset between start addresses of successive specified ranges. Use of the range prefetch instruction helps to improve programmability and improve the balance between prefetch coverage and circuit area of the prefetch circuitry.