公开(公告)号：US20220374240A1

公开(公告)日：2022-11-24

申请号：US17326864

申请日：2021-05-21

Applicant: Arm Limited

Inventor： Damian MAIORANO ,  Luca NASSI ,  Cédric Denis Robert AIRAUD ,  Christophe Laurent CARBONNE ,  Jocelyn François Orion JAUBERT ,  Pasquale RANONE

IPC: G06F9/38 ,  G06F9/30 ,  G06F11/07

Abstract: Data processing circuitry comprises out-of-order instruction execution circuitry; register mapping circuitry to map zero or more architectural processor registers relating to execution of that program instruction to respective ones of a set of physical processor registers; commit circuitry to commit, in a program code order, the results of executed program instructions, the commit circuitry being configured to access a data store which stores register tag data to indicate which physical registers mapped by the register mapping circuitry relate to a given program instruction; fault detection circuitry to detect a memory access fault in respect of a vector memory access operation and to generate fault indication data indicative of an element earliest in the element order for which a memory access fault was detected; a fault indication register to store the fault indication data, in which the register mapping circuitry is configured to generate a register mapping for a program instruction for any architectural processor registers relating to execution of that program instruction other than the fault indication register; and control circuitry to encode the fault indication data, applicable to a program instruction not yet committed by the commit circuitry, to register tag data associated with that program instruction.