公开(公告)号：US20250004945A1

公开(公告)日：2025-01-02

申请号：US18343971

申请日：2023-06-29

Applicant: Arm Limited

Inventor： Vladimir VASEKIN ,  Vincent REZARD ,  Antony John PENTON ,  Cédric Denis Robert AIRAUD

IPC: G06F12/0862

Abstract: An apparatus comprises associating circuitry to associate an indirect prefetch condition with a memory access request when hint information indicates that the data to be accessed in response to the memory access request is address indicating data which is to be used to generate a second address for a subsequent memory access request. A second address can be generated using the address indicating data, and a prefetch memory access request can be issued to seek to make data at the second address available in the associated cache.

公开(公告)号：US20230342154A1

公开(公告)日：2023-10-26

申请号：US17724600

申请日：2022-04-20

Applicant: Arm Limited

Inventor： Luca MARONCELLI ,  Harvin IRIAWAN ,  Peter Raphael EID ,  Cédric Denis Robert AIRAUD

IPC: G06F9/38

CPC classification number: G06F9/3802 ,  G06F9/3851

Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry, prefetch circuitry and prefetch metadata storage comprising a plurality of entries. Metadata items, each associated with a given stream of instructions, are stored in the prefetch metadata storage. Responsive to a given entry of the plurality of entries being associated with the given stream associated with a given metadata item, the given entry is updated. Responsive to no entry of the plurality of entries being associated with the given stream associated with a given metadata item, an entry is selected according to a default replacement policy, the given stream is allocated thereto, and the selected entry is updated based on the given metadata item. Responsive to a switch condition being met, the default selection policy is switched to an alternative selection policy comprising locking one or more entries by preventing allocation of streams to the locked entries.

公开(公告)号：US20140181478A1

公开(公告)日：2014-06-26

申请号：US13723974

申请日：2012-12-21

Applicant: ARM LIMITED

Inventor： Cédric Denis Robert AIRAUD ,  Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Guillaume Schon

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30014 ,  G06F9/30141 ,  G06F9/3857

Abstract: Within a processing pipeline 14, issue control circuitry 12 serves to arbitrate write port availability when floating point multiplication instructions are issued into a floating point pipeline 14. If not operating in a flush-to-zero mode, then depending upon the output operands generated denormal handling may or may not be required. A pessimistic assumption is made upon issue that denormal handling will be required and accordingly the write port reserved is a first predetermined number of processing cycles after the start cycle to take account of use of the denormal handling pipeline stage 20. Partway along the processing pipeline 14, state becomes available which indicates whether or not denormal handling is actually required. If denormal handling is not required and a write port is available one processing cycle earlier, then bypass circuitry 22 serves to bypass the denormal handling pipeline stage 20 such that the output operand will be written to the register bank 16 one processing cycle earlier. Write port usage is tracked by a write port usage scoreboard 26 which is both read and updated by the bypass circuitry 22 when re-arbitrating write port availability partway through a floating point multiplication instruction passing along the pipeline 14.

Abstract translation: 在处理流水线14内，发布控制电路12用于在将浮点乘法指令发布到浮点流水线14时仲裁写端口的可用性。如果不是以冲零模式工作，则根据产生的非正规输出操作数 处理可能或可能不需要。 在需要进行异常处理的问题上做出悲观的假设，因此，保留的写入端口是在开始周期之后的第一预定数量的处理周期，以考虑使用异常处理流水线级20。沿着处理流水线14 ，状态变为可用，其指示是否实际需要异常处理。 如果不需要异常处理并且写入端口可用于处理周期之前，则旁路电路22用于绕过异常处理流水线级20，使得输出操作数将被更早地写入一个处理周期的寄存器组16。 写端口使用记录板26由写入端口使用记分板26跟踪，当通过沿管线14传送的浮点乘法指令重新协商写入端口可用性时，旁路电路22读取和更新。

公开(公告)号：US20240241723A1

公开(公告)日：2024-07-18

申请号：US18096141

申请日：2023-01-12

Applicant: Arm Limited

Inventor： Luca NASSI ,  Geoffray Matthieu LACOURBA ,  Cédric Denis Robert AIRAUD ,  Albin Pierrick TONNERRE

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30098 ,  G06F9/30094 ,  G06F9/384

Abstract: A data processing apparatus is provided. Instruction send circuitry sends an instruction to an external processor to be executed by the external processor. Allocation circuitry allocates a specified one of several registers for a result of the instruction having been executed on the external processor and data receive circuitry receives the result of the instruction having been executed on the external processor and stores the result in the specified one of the several registers. In response to a condition being met: the specified one of the several registers is dereserved prior to the result being received by the data receive circuitry, and the result is discarded by the data receive circuitry when the result is received by the data receive circuitry.

公开(公告)号：US20220229783A1

公开(公告)日：2022-07-21

申请号：US17153147

申请日：2021-01-20

Applicant: Arm Limited

Inventor： Frederic Claude Marie PIRY ,  Natalya BONDARENKO ,  Cédric Denis Robert AIRAUD ,  Geoffray Matthieu LACOURBA

IPC: G06F12/126 ,  G06F12/02 ,  G06K9/62

Abstract: A technique is provided for training a prediction apparatus. The apparatus has an input interface for receiving a sequence of training events indicative of program instructions, and identifier value generation circuitry for performing an identifier value generation function to generate, for a given training event received at the input interface, an identifier value for that given training event. The identifier value generation function is arranged such that the generated identifier value is dependent on at least one register referenced by a program instruction indicated by that given training event. Prediction storage is provided with a plurality of training entries, where each training entry is allocated an identifier value as generated by the identifier value generation function, and is used to maintain training data derived from training events having that allocated identifier value. Matching circuitry is then responsive to the given training event to detect whether the prediction storage has a matching training entry (i.e. an entry whose allocated identifier value matches the identifier value for the given training event). If so, it causes the training data in the matching training entry to be updated in dependence on the given training event.

公开(公告)号：US20210026772A1

公开(公告)日：2021-01-28

申请号：US16521665

申请日：2019-07-25

Applicant: Arm Limited

Inventor： Xiaoyang SHEN ,  Yohann Fred Arifidy RABEFARIHY ,  Cédric Denis Robert AIRAUD ,  Rémi Marius TEYSSIER

IPC: G06F12/0875 ,  G06F12/14 ,  G06F12/0895 ,  G06F9/30

Abstract: An apparatus is provided for determining, for use in a tag-guarded memory, a selected tag value from a plurality of tag values. The apparatus comprises ordered list generation circuitry to receive an excluded tag vector comprising a plurality of fields, where each field is associated with a tag value and identifies whether the associated tag value is excluded from use. The ordered list generation circuitry is arranged to generate, from the excluded tag vector, an ordered list of non-excluded tag values. The apparatus further comprises count determination circuitry to determine, using the excluded tag vector and an identified start tag value, a count value indicative of a number of non-excluded tag values occurring in a region of the excluded tag vector bounded by an initial field and a field corresponding to the start tag value. The apparatus also comprises tag selection circuitry to determine the selected tag value from the ordered list based on the count value and an identified offset which indicates a required number of non-excluded tag values between the start tag value and the selected tag value.

公开(公告)号：US20240289130A1

公开(公告)日：2024-08-29

申请号：US18174207

申请日：2023-02-24

Applicant: Arm Limited

Inventor： Xiaoyang SHEN ,  Zichao XIE ,  Cédric Denis Robert AIRAUD ,  Grégorie MARTIN

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30098 ,  G06F9/3826 ,  G06F9/3869

Abstract: A data processing apparatus comprises operand routing circuitry configured to prepare operands for processing, and a plurality of processing elements. Each processing element comprises receiving circuitry, processing circuitry, and transmitting circuitry. A group of coupled processing elements comprises a first processing element configured to receive operands from the operand routing circuitry and one or more further processing elements for which the receiving circuitry is coupled to the transmitting circuitry of another processing element in the group. The apparatus also comprises timing circuitry, configured to selectively delay transmission of operands within the group of coupled processing elements to cause operations performed by the group of coupled processing elements to be staggered.

公开(公告)号：US20220374240A1

公开(公告)日：2022-11-24

申请号：US17326864

申请日：2021-05-21

Applicant: Arm Limited

Inventor： Damian MAIORANO ,  Luca NASSI ,  Cédric Denis Robert AIRAUD ,  Christophe Laurent CARBONNE ,  Jocelyn François Orion JAUBERT ,  Pasquale RANONE

IPC: G06F9/38 ,  G06F9/30 ,  G06F11/07

Abstract: Data processing circuitry comprises out-of-order instruction execution circuitry; register mapping circuitry to map zero or more architectural processor registers relating to execution of that program instruction to respective ones of a set of physical processor registers; commit circuitry to commit, in a program code order, the results of executed program instructions, the commit circuitry being configured to access a data store which stores register tag data to indicate which physical registers mapped by the register mapping circuitry relate to a given program instruction; fault detection circuitry to detect a memory access fault in respect of a vector memory access operation and to generate fault indication data indicative of an element earliest in the element order for which a memory access fault was detected; a fault indication register to store the fault indication data, in which the register mapping circuitry is configured to generate a register mapping for a program instruction for any architectural processor registers relating to execution of that program instruction other than the fault indication register; and control circuitry to encode the fault indication data, applicable to a program instruction not yet committed by the commit circuitry, to register tag data associated with that program instruction.

公开(公告)号：US20220308880A1

公开(公告)日：2022-09-29

申请号：US17209515

申请日：2021-03-23

Applicant: Arm Limited

Inventor： Natalya BONDARENKO ,  Stefano GHIGGINI ,  Geoffray Matthieu LACOURBA ,  Cédric Denis Robert AIRAUD

IPC: G06F9/38 ,  G06N20/00

Abstract: The invention provides a data processing apparatus and a data processing method for generating prefetches of data for use during execution of instructions by processing circuitry. The prefetches that are generated are based on a nested prefetch pattern. The nested prefetch pattern comprises a first pattern and a second pattern. The first pattern is defined by a first address offset between sequentially accessed addresses and a first observed number of the sequentially accessed addresses separated by the first address offset. The second pattern is defined by a second address offset between sequential iterations of the first pattern and a second observed number of the sequential iterations of the first pattern separated by the second address offset.

公开(公告)号：US20200065109A1

公开(公告)日：2020-02-27

申请号：US16524667

申请日：2019-07-29

Applicant: Arm Limited

Inventor： Xiaoyang SHEN ,  Damien Robin MARTIN ,  Cédric Denis Robert AIRAUD ,  Luca NASSI ,  François DONATI

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/355 ,  G06F9/22

Abstract: An apparatus has a processing pipeline, and first and second register files. A temporary-register-using instruction is supported which controls the pipeline to perform an operation using a temporary variable derived from an operand stored in the first register file. In response to the instruction, when a predetermined condition is not satisfied, the pipeline processes at least one register move micro-operation to transfer data from the at least one source register of the first register file to at least one newly allocated temporary register of the second register file. When the condition is satisfied, the operation can be performed using a temporary variable already stored in the temporary register of the second register file used by an earlier temporary-register-using instruction specifying the same source register for determining the temporary variable, in the absence of an intervening instruction for rewriting the source register.