公开(公告)号：US20220357953A1

公开(公告)日：2022-11-10

申请号：US17315737

申请日：2021-05-10

Applicant: Arm Limited

Inventor： Jaekyu LEE ,  Yasuo ISHII ,  Krishnendra NATHELLA ,  Dam SUNWOO

IPC: G06F9/38 ,  G06F9/30

Abstract: A data processing apparatus is provided. It includes control flow detection prediction circuitry that performs a presence prediction of whether a block of instructions contains a control flow instruction. A fetch queue stores, in association with prediction information, a queue of indications of the instructions and the prediction information comprises the presence prediction. An instruction cache stores fetched instructions that have been fetched according to the fetch queue. Post-fetch correction circuitry receives the fetched instructions prior to the fetched instructions being received by decode circuitry, the post-fetch correction circuitry includes analysis circuitry that causes the fetch queue to be at least partly flushed in dependence on a type of a given fetched instruction and the prediction information associated with the given fetched instruction.

公开(公告)号：US20210067335A1

公开(公告)日：2021-03-04

申请号：US16550598

申请日：2019-08-26

Applicant: Arm Limited

Inventor： Jaekyu LEE ,  Yasuo ISHII ,  Dam SUNWOO

IPC: H04L9/08

Abstract: A data processing apparatus is provided that includes storage circuitry. Communication circuitry responds to an access request comprising a requested index with an access response comprising requested data. Coding circuitry performs a coding operation using a current key to: translate the requested index to an encoded index of the storage circuitry at which the requested data is stored or to translate encoded data stored at the requested index of the storage circuitry to the requested data. The current key is based on an execution environment. Update circuitry performs an update, in response to the current key being changed, of: the encoded index of the storage circuitry at which the requested data is stored or the encoded data.

公开(公告)号：US20220035679A1

公开(公告)日：2022-02-03

申请号：US16943117

申请日：2020-07-30

Applicant: Arm Limited

Inventor： Dam SUNWOO ,  Supreet JELOKA ,  Saurabh Pijuskumar SINHA ,  Jaekyu LEE ,  Jose Alberto JOAO ,  Krishnendra NATHELLA

IPC: G06F9/50 ,  G06N20/00 ,  G06N5/04

Abstract: A method for controlling hardware resource configuration for a processing system comprises obtaining performance monitoring data indicative of processing performance associated with workloads to be executed on the processing system, providing a trained machine learning model with input data depending on the performance monitoring data; and based on an inference made from the input data by the trained machine learning model, setting control information for configuring the processing system to control an amount of hardware resource allocated for use by at least one processor core. A corresponding method of training the model is provided. This is particularly useful for controlling inter-core borrowing of resource between processor cores in a multi-core processing system, where resource is borrowed between respective cores, e.g. cores on different layers of a 3D integrated circuit.

公开(公告)号：US20210373889A1

公开(公告)日：2021-12-02

申请号：US16887442

申请日：2020-05-29

Applicant: Arm Limited

Inventor： Lingzhe CAI ,  Krishnendra NATHELLA ,  Jaekyu LEE ,  Dam SUNWOO

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52 ,  G06F9/54 ,  G06F12/0862 ,  G06F12/1027

Abstract: An apparatus and method is provided, the apparatus comprising a processor pipeline to execute instructions, a cache structure to store information for reference by the processor pipeline when executing said instructions; and pref etch circuitry to issue prefetch requests to the cache structure to cause the cache structure to prefetch information into the cache structure in anticipation of a demand request for that information being issued to the cache structure by the processor pipeline. The processor pipeline is arranged to issue a trigger to the prefetch circuitry on detection of a given event that will result in a reduced level of demand requests being issued by the processor pipeline, and the prefetch circuitry is configured to control issuing of pref etch requests in dependence on reception of the trigger.