公开(公告)号：US20200097411A1

公开(公告)日：2020-03-26

申请号：US16140625

申请日：2018-09-25

Applicant: Arm Limited

Inventor： Joseph Michael PUSDESRIS ,  Miles Robert DOOLEY ,  Alexander Cole SHULYAK ,  Krishnendra NATHELLA ,  Dam SUNWOO

IPC: G06F12/0862 ,  G06F5/06 ,  G06F9/30

Abstract: Apparatuses and methods for prefetch generation are disclosed. Prefetching circuitry receives addresses specified by load instructions and can cause retrieval of a data value from an address before that address is received. Stride determination circuitry determines stride values as a difference between a current address and a previously received address. Plural stride values corresponding to a sequence of received addresses are determined. Multiple stride storage circuitry stores the plurality of stride values determined by the stride determination circuitry. New address comparison circuitry determines whether a current address corresponds to a matching stride value based on the plurality of stride values stored in the multiple stride storage circuitry. Prefetch initiation circuitry can causes a data value to be retrieved from a further address, wherein the further address is the current address modified by the matching stride value of the plurality of stride values. By the use of multiple stride values, more complex load address patterns can be prefetched.

公开(公告)号：US20220357953A1

公开(公告)日：2022-11-10

申请号：US17315737

申请日：2021-05-10

Applicant: Arm Limited

Inventor： Jaekyu LEE ,  Yasuo ISHII ,  Krishnendra NATHELLA ,  Dam SUNWOO

IPC: G06F9/38 ,  G06F9/30

Abstract: A data processing apparatus is provided. It includes control flow detection prediction circuitry that performs a presence prediction of whether a block of instructions contains a control flow instruction. A fetch queue stores, in association with prediction information, a queue of indications of the instructions and the prediction information comprises the presence prediction. An instruction cache stores fetched instructions that have been fetched according to the fetch queue. Post-fetch correction circuitry receives the fetched instructions prior to the fetched instructions being received by decode circuitry, the post-fetch correction circuitry includes analysis circuitry that causes the fetch queue to be at least partly flushed in dependence on a type of a given fetched instruction and the prediction information associated with the given fetched instruction.

公开(公告)号：US20190102388A1

公开(公告)日：2019-04-04

申请号：US16207241

申请日：2018-12-03

Applicant: ARM LIMITED

Inventor： Mitchell Bryan HAYENGA ,  Curtis Glenn DUNHAM ,  Dam SUNWOO

IPC: G06F17/30 ,  G06F12/0875

Abstract: An apparatus has processing circuitry for processing instructions from multiple threads. A storage structure is shared between the threads and has a number of entries. Indexing circuitry generates a target index value identifying an entry of the storage structure to be accessed in response to a request from the processing circuitry specifying a requested index value corresponding to information to be accessed from the storage structure. The indexing circuitry generates the target index value as a function of the requested index value and a key value selected depending on which of the threads trigger the request. The key value for at least one of the threads is updated from time to time.

公开(公告)号：US20220035679A1

公开(公告)日：2022-02-03

申请号：US16943117

申请日：2020-07-30

Applicant: Arm Limited

Inventor： Dam SUNWOO ,  Supreet JELOKA ,  Saurabh Pijuskumar SINHA ,  Jaekyu LEE ,  Jose Alberto JOAO ,  Krishnendra NATHELLA

IPC: G06F9/50 ,  G06N20/00 ,  G06N5/04

Abstract: A method for controlling hardware resource configuration for a processing system comprises obtaining performance monitoring data indicative of processing performance associated with workloads to be executed on the processing system, providing a trained machine learning model with input data depending on the performance monitoring data; and based on an inference made from the input data by the trained machine learning model, setting control information for configuring the processing system to control an amount of hardware resource allocated for use by at least one processor core. A corresponding method of training the model is provided. This is particularly useful for controlling inter-core borrowing of resource between processor cores in a multi-core processing system, where resource is borrowed between respective cores, e.g. cores on different layers of a 3D integrated circuit.

公开(公告)号：US20210373889A1

公开(公告)日：2021-12-02

申请号：US16887442

申请日：2020-05-29

Applicant: Arm Limited

Inventor： Lingzhe CAI ,  Krishnendra NATHELLA ,  Jaekyu LEE ,  Dam SUNWOO

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/52 ,  G06F9/54 ,  G06F12/0862 ,  G06F12/1027

Abstract: An apparatus and method is provided, the apparatus comprising a processor pipeline to execute instructions, a cache structure to store information for reference by the processor pipeline when executing said instructions; and pref etch circuitry to issue prefetch requests to the cache structure to cause the cache structure to prefetch information into the cache structure in anticipation of a demand request for that information being issued to the cache structure by the processor pipeline. The processor pipeline is arranged to issue a trigger to the prefetch circuitry on detection of a given event that will result in a reduced level of demand requests being issued by the processor pipeline, and the prefetch circuitry is configured to control issuing of pref etch requests in dependence on reception of the trigger.

公开(公告)号：US20240370266A1

公开(公告)日：2024-11-07

申请号：US18312052

申请日：2023-05-04

Applicant: Arm Limited

Inventor： Alexander Cole SHULYAK ,  Yasuo ISHII ,  Dam SUNWOO ,  Houdhaifa BOUZGUARROU

IPC: G06F9/38 ,  G06F12/0875

Abstract: An apparatus is provided having pointer storage to store pointer values for a plurality of pointers, with the pointer values of the pointers being differentially incremented in response to a series of increment events. Tracker circuitry maintains a plurality of tracker entries, each tracker entry identifying a control flow instruction and a current active pointer (from amongst the pointers) to be associated with that control flow instruction. Cache circuitry maintains a plurality of cache entries, each cache entry storing a resolved behaviour of an instance of a control flow instruction identified by a tracker entry along with an associated tag value generated when the resolved behaviour was allocated into that cache entry. For a given entry the associated tag value may be generated in dependence on an address indication of the control flow instruction whose resolved behaviour is being stored in that entry and the current active pointer associated with that control flow instruction. Prediction circuitry is responsive to a prediction trigger associated with a replay of a given instance of a given control flow instruction identified by a tracker entry, to cause a lookup operation to be performed by the cache circuitry using a comparison tag value generated in dependence on the address indication of the given control flow instruction and the current active pointer. In the event of a hit being detected in a given cache entry, the resolved behaviour stored in the given cache entry is used as the predicted behaviour of the given instance of the given control flow instruction, provided a prediction confidence metric is met.

公开(公告)号：US20210067335A1

公开(公告)日：2021-03-04

申请号：US16550598

申请日：2019-08-26

Applicant: Arm Limited

Inventor： Jaekyu LEE ,  Yasuo ISHII ,  Dam SUNWOO

IPC: H04L9/08

Abstract: A data processing apparatus is provided that includes storage circuitry. Communication circuitry responds to an access request comprising a requested index with an access response comprising requested data. Coding circuitry performs a coding operation using a current key to: translate the requested index to an encoded index of the storage circuitry at which the requested data is stored or to translate encoded data stored at the requested index of the storage circuitry to the requested data. The current key is based on an execution environment. Update circuitry performs an update, in response to the current key being changed, of: the encoded index of the storage circuitry at which the requested data is stored or the encoded data.

公开(公告)号：US20170286421A1

公开(公告)日：2017-10-05

申请号：US15086866

申请日：2016-03-31

Applicant: ARM LIMITED

Inventor： Mitchell Bryan HAYENGA ,  Curtis Glenn DUNHAM ,  Dam SUNWOO

IPC: G06F17/30 ,  G06F12/08

CPC classification number: G06F17/3033 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1027 ,  G06F17/30132 ,  G06F21/75 ,  G06F2212/6032

Abstract: An apparatus has processing circuitry for processing instructions from multiple threads. A storage structure is shared between the threads and has a number of entries. Indexing circuitry generates a target index value identifying an entry of the storage structure to be accessed in response to a request from the processing circuitry specifying a requested index value corresponding to information to be accessed from the storage structure. The indexing circuitry generates the target index value as a function of the requested index value and a key value selected depending on which of the threads trigger the request. The key value for at least one of the threads is updated from time to time.