公开(公告)号：US20240329999A1

公开(公告)日：2024-10-03

申请号：US18129979

申请日：2023-04-03

Applicant: Arm Limited

Inventor： Chang Joo LEE ,  Jason Lee SETTER ,  Julia Kay LANIER ,  Michael Brian SCHINZLER ,  Yasuo ISHII

IPC: G06F9/38

CPC classification number: G06F9/3806 ,  G06F9/3861 ,  G06F9/3802

Abstract: An apparatus is provided for limiting the effective utilisation of an instruction fetch queue. The instruction fetch entries are used to control the prefetching of instructions from memory, such that those instructions are stored in an instruction cache prior to being required by execution circuitry while executing a program. By limiting the effective utilisation of the instruction fetch queue, fewer instructions will be prefetched and fewer instructions will be allocated to the instruction cache, thus causing fewer evictions from the instruction cache. In the event that the instruction fetch entries are for instructions that are unnecessary to the program, the pollution of the instruction cache with these unnecessary instructions can be mitigated.