公开(公告)号：US20230176979A1

公开(公告)日：2023-06-08

申请号：US17541007

申请日：2021-12-02

Applicant: Arm Limited

Inventor： Alexander Cole SHULYAK ,  Joseph Michael PUSDESRIS ,  . ABHISHEK RAJA ,  Karthik SUNDARAM ,  Anoop Ramachandra IYER ,  Michael Brian SCHINZLER ,  James David DUNDAS ,  Yasuo ISHII

IPC: G06F12/1027

CPC classification number: G06F12/1027

Abstract: An apparatus comprises memory management circuitry to perform a translation table walk for a target address of a memory access request and to signal a fault in response to the translation table walk identifying a fault condition for the target address, prefetch circuitry to generate a prefetch request to request prefetching of information associated with a prefetch target address to a cache; and faulting address prediction circuitry to predict whether the memory management circuitry would identify the fault condition for the prefetch target address if the translation table walk was performed by the memory management circuitry for the prefetch target address. In response to a prediction that the fault condition would be identified for the prefetch target address, the prefetch circuitry suppresses the prefetch request and the memory management circuitry prevents the translation table walk being performed for the prefetch target address of the prefetch request.

公开(公告)号：US20220342671A1

公开(公告)日：2022-10-27

申请号：US17241365

申请日：2021-04-27

Applicant: Arm Limited

Inventor： Michael Brian SCHINZLER ,  Muhammad Umar FAROOQ ,  Yasuo ISHII

IPC: G06F9/38 ,  G06F9/32 ,  G06F9/30

Abstract: Aspects of the present disclosure relate an apparatus comprising fetch circuitry and instruction storage circuitry. The fetch circuitry is to fetch instructions for execution by execution circuitry. The instruction storage circuitry is to store temporary copies of fetched instructions. The fetch circuitry is configured to preferentially fetch instructions from the instruction storage circuitry. The instruction storage circuitry is configured to, responsive to a storage condition being met, begin storing copies of consecutive fetched instructions, the storage condition indicating a utility of a current fetched instruction; and to, responsive to determining that a number of said stored consecutive instructions has reached a storage threshold, cease storing copies of subsequent fetched instructions.

公开(公告)号：US20210019150A1

公开(公告)日：2021-01-21

申请号：US16514124

申请日：2019-07-17

Applicant: Arm Limited

Inventor： Michael Brian SCHINZLER ,  Michael FILIPPO ,  Yasuo ISHII

IPC: G06F9/38 ,  G06F9/30

Abstract: Apparatuses for data processing and methods of data processing are provided. A data processing apparatus performs data processing operations in response to a sequence of instructions including performing speculative execution of at least some of the sequence of instructions. In response to a branch instruction the data processing apparatus predicts whether or not the branch is taken or not taken further speculative instruction execution is based on that prediction. A path speculation cost is calculated in dependence on a number of recently flushed instructions and a rate at which speculatively executed instructions are issued may be modified based on the path speculation cost.

公开(公告)号：US20250076962A1

公开(公告)日：2025-03-06

申请号：US18458339

申请日：2023-08-30

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGUARROU ,  Michael Brian SCHINZLER

IPC: G06F1/3287

Abstract: A data processing apparatus is provided. It includes first history storage circuitry that stores control flow information of control flow instructions. Second history storage circuitry stores a subset of the control flow information by considering a subset of the control flow instructions. Prediction circuitry produces a prediction for a specific one of the control flow instructions based on the subset of the control flow information and power control circuitry performs a determination of an extent to which the subset of the control flow information matches the control flow information and disables the prediction circuitry in dependence on a result of the determination.

公开(公告)号：US20250068939A1

公开(公告)日：2025-02-27

申请号：US18455053

申请日：2023-08-24

Applicant: ARM Limited

Inventor： Houdhaifa BOUZGUARROU ,  Rami Mohammad AL SHEIKH ,  Michael Brian SCHINZLER

IPC: G06N5/022

Abstract: Combiner circuitry generates a combined prediction associated with a given address based on combining respective sets of prediction information generated by two or more predictors. Predictor control circuitry determines, based on a lookup of a prediction input address in a combiner hint data structure, whether a second predictor lookup suppression condition is satisfied for the prediction input address indicating that the combined prediction that would be determined by the combiner circuitry for the prediction input address is likely to be derivable from a prediction outcome predicted by the first predictor for the prediction input address. If this condition is satisfied, a lookup of the second predictor is suppressed and the prediction associated with the prediction input address is generated based on the prediction outcome predicted by the first predictor for the prediction input address.

公开(公告)号：US20220107807A1

公开(公告)日：2022-04-07

申请号：US17064983

申请日：2020-10-07

Applicant: Arm Limited

Inventor： Michael Brian SCHINZLER ,  Yasuo ISHII ,  Muhammad Umar FAROOQ ,  Jason Lee SETTER

IPC: G06F9/30 ,  G06F12/0875 ,  G06F9/38

Abstract: An apparatus and method are provided for processing instructions fetched from memory. Decode circuitry is used to decode the fetched instructions in order to produce decoded instructions, and downstream circuitry then processes the decoded instructions in order to perform the operations specified by those decoded instructions. Dispatch circuitry is arranged to dispatch to the downstream circuitry up to N decoded instructions per dispatch cycle, and is arranged to determine, based on a given candidate sequence of decoded instructions being considered for dispatch in a given dispatch cycle, whether at least one resource conflict within the downstream circuitry would occur in the event that the given candidate sequence of decoded instructions is dispatched in the given dispatch cycle. The dispatch circuitry has resource checking circuitry arranged, by default, to perform a resource checking operation during the given dispatch cycle to generate, for the given candidate sequence of decoded instructions, resource conflict information used to determine whether a resource conflict would occur. Resource conflict information cache storage is provided to maintain, for one or more sequences of decoded instructions, associated resource conflict information. In the event that the given candidate sequence matches one of the sequences for which associated resource conflict information is cached, the dispatch circuitry employs the associated cached resource conflict information to determine whether a resource conflict would occur, instead of invoking the resource checking circuitry to perform the resource checking operation.

公开(公告)号：US20240329999A1

公开(公告)日：2024-10-03

申请号：US18129979

申请日：2023-04-03

Applicant: Arm Limited

Inventor： Chang Joo LEE ,  Jason Lee SETTER ,  Julia Kay LANIER ,  Michael Brian SCHINZLER ,  Yasuo ISHII

IPC: G06F9/38

CPC classification number: G06F9/3806 ,  G06F9/3861 ,  G06F9/3802

Abstract: An apparatus is provided for limiting the effective utilisation of an instruction fetch queue. The instruction fetch entries are used to control the prefetching of instructions from memory, such that those instructions are stored in an instruction cache prior to being required by execution circuitry while executing a program. By limiting the effective utilisation of the instruction fetch queue, fewer instructions will be prefetched and fewer instructions will be allocated to the instruction cache, thus causing fewer evictions from the instruction cache. In the event that the instruction fetch entries are for instructions that are unnecessary to the program, the pollution of the instruction cache with these unnecessary instructions can be mitigated.

公开(公告)号：US20240095034A1

公开(公告)日：2024-03-21

申请号：US17949874

申请日：2022-09-21

Applicant: Arm Limited

Inventor： James David DUNDAS ,  Yasuo ISHII ,  Michael Brian SCHINZLER

IPC: G06F9/38

CPC classification number: G06F9/3838 ,  G06F9/3861

Abstract: A data processing apparatus includes control flow prediction circuitry that generates a control flow prediction in respect of a group of one or more instructions. Storage circuitry used by the control flow prediction circuitry stores data in association with groups of instructions used to generate the control flow prediction for each of the groups of instructions. Control flow prediction update circuitry inserts new data into the storage circuitry in association with a new group of one or more instructions in dependence on one or more conditions being met when a miss occurs for the group of one or more instructions in the storage circuitry.

公开(公告)号：US20230385066A1

公开(公告)日：2023-11-30

申请号：US17752060

申请日：2022-05-24

Applicant: Arm Limited

Inventor： Houdhaifa BOUZGUARROU ,  Michael Brian SCHINZLER ,  Yasuo ISHII ,  Jatin BHARTIA ,  Sumanth CHENGAD RAGHU

IPC: G06F9/38 ,  G06F1/03

CPC classification number: G06F9/3848 ,  G06F9/3844 ,  G06F9/3806 ,  G06F1/03

Abstract: A first type of prediction, for controlling execution of at least one instruction by processing circuitry, is based at least on a first prediction table storing prediction information looked up based on at least a first portion of branch history information stored in branch history storage corresponding to a first predetermined number of branches. In response to detecting an execution state switch of the processing circuitry from a first execution state to a second, more privileged, execution state, use of the first prediction table for determining the first type of prediction is disabled. In response to detecting that a number of branches causing an update to the branch history storage since the execution state switch is greater than or equal to the first predetermined number, use of the first prediction table in determining the first type of prediction is re-enabled.

公开(公告)号：US20250077233A1

公开(公告)日：2025-03-06

申请号：US18459602

申请日：2023-09-01

Applicant: ARM Limited

Inventor： Houdhaifa BOUZGUARROU ,  Michael Brian SCHINZLER

IPC: G06F9/38 ,  G06F9/30

Abstract: A data processing apparatus is provided. It includes history storage circuitry that stores historic data of instructions and prediction circuitry that predicts a historic datum of a specific instruction based on subsets of the historic data of the instructions. The history storage circuitry overwrites the historic data of one of the instructions to form a corrupted instruction datum and at least one of the subsets of the historic data of the instructions includes the corrupted historic datum.