公开(公告)号：US11086781B2

公开(公告)日：2021-08-10

申请号：US16658463

申请日：2019-10-21

Applicant: Arm Limited

Inventor： Natalya Bondarenko ,  Florent Begon ,  Nathanael Premillieu ,  Pierre Marcel Laurent

IPC: G06F12/08 ,  G06F12/0862 ,  G06F12/0811 ,  G06F12/0891

Abstract: Examples of the present disclosure relate to an apparatus comprising processing circuitry to perform data processing operations and a hierarchical cache structure. The cache structure comprises a plurality of cache levels to store data for access by the processing circuitry, and includes a highest cache level arranged to receive data requests directly from the processing circuitry. The apparatus comprises a plurality of prefetch units, each prefetch unit being associated with a cache level and being arranged to prefetch data into the associated cache level in anticipation of the processing circuitry requiring the data, wherein: each cache level has a plurality of entries and is arranged to maintain prefetch tag information for each entry which, when a given entry contains prefetched data, indicates which prefetch unit of that cache level and/or of a lower cache level prefetched that data; and each cache level is arranged, responsive to a data request from a higher cache level, to provide to the higher cache level the requested data and the prefetch tag information corresponding to the requested data. The apparatus further comprises accuracy information storage to: maintain accuracy inferring information for each prefetch unit; and when given data is evicted from a cache level, update the accuracy inferring information based on the prefetch tag information.