公开(公告)号：US11507475B2

公开(公告)日：2022-11-22

申请号：US16475487

申请日：2017-12-12

Applicant: Arm Limited

Inventor： Matthias Lothar Boettcher ,  Mbou Eyole ,  Nathanael Premillieu

IPC: G06F11/00 ,  G06F11/16 ,  G06F9/30 ,  G06F11/07 ,  G06F9/38

Abstract: A data processing apparatus (2) has scalar processing circuitry (32-42) and vector processing circuitry (38, 40, 42). When executing main scalar processing on the scalar processing circuitry (32-42), or main vector processing using a subset of said plurality of lanes on the vector processing circuitry (38, 40, 42), checker processing is executed using at least one lane of the plurality of lanes on the vector processing circuitry (38, 40, 42), the checker processing comprising operations corresponding to at least part of the main scalar/vector processing. Errors can then be detected based on a comparison of an outcome of the main processing and an outcome of the checker processing. This provides a technique for achieving functional safety in a high end processor with better performance and reduced hardware cost compared to a dual/triple core lockstep approach.

公开(公告)号：US11314514B2

公开(公告)日：2022-04-26

申请号：US15741303

申请日：2016-06-23

Applicant: ARM Limited

Inventor： Nigel John Stephens ,  Grigorios Magklis ,  Alejandro Martinez Vicente ,  Nathanael Premillieu

IPC: G06F1/00 ,  G06F9/30

Abstract: A data processing system 2 supporting vector processing operations uses scaling vector length querying instructions. The scaling vector length querying instructions return a result which is dependent upon a number of elements in a vector for a variable vector element size specified by the instruction and multiplied by a scaling value specified by the instruction. The scaling vector length querying instructions may be in the form of count instructions, increment instructions or decrement instructions. The instructions may include a pattern constraint applying a constraint, such as modulo(M) or power of 2 to the partial result value representing the number of vector elements provided for the register element size specified for the instruction.

公开(公告)号：US11086781B2

公开(公告)日：2021-08-10

申请号：US16658463

申请日：2019-10-21

Applicant: Arm Limited

Inventor： Natalya Bondarenko ,  Florent Begon ,  Nathanael Premillieu ,  Pierre Marcel Laurent

IPC: G06F12/08 ,  G06F12/0862 ,  G06F12/0811 ,  G06F12/0891

Abstract: Examples of the present disclosure relate to an apparatus comprising processing circuitry to perform data processing operations and a hierarchical cache structure. The cache structure comprises a plurality of cache levels to store data for access by the processing circuitry, and includes a highest cache level arranged to receive data requests directly from the processing circuitry. The apparatus comprises a plurality of prefetch units, each prefetch unit being associated with a cache level and being arranged to prefetch data into the associated cache level in anticipation of the processing circuitry requiring the data, wherein: each cache level has a plurality of entries and is arranged to maintain prefetch tag information for each entry which, when a given entry contains prefetched data, indicates which prefetch unit of that cache level and/or of a lower cache level prefetched that data; and each cache level is arranged, responsive to a data request from a higher cache level, to provide to the higher cache level the requested data and the prefetch tag information corresponding to the requested data. The apparatus further comprises accuracy information storage to: maintain accuracy inferring information for each prefetch unit; and when given data is evicted from a cache level, update the accuracy inferring information based on the prefetch tag information.

公开(公告)号：US10776274B2

公开(公告)日：2020-09-15

申请号：US15910122

申请日：2018-03-02

Applicant: Arm Limited

Inventor： Lucas Garcia ,  Geoffray Matthieu Lacourba ,  Natalya Bondarenko ,  Nathanael Premillieu

IPC: G06F12/00 ,  G06F12/0862

Abstract: Data processing circuitry comprises a cache memory to cache a subset of data elements from a main memory; a processing element to execute program code to access data elements having respective memory addresses, the processing element being configured to access the data elements in the cache memory and, in the case of a cache miss, to fetch the data elements from the main memory; prefetch circuitry, responsive to an access to a current data element, to initiate prefetching into the cache memory of a data element at a memory address defined by a current offset value relative to the address of the current data element; and offset value selection circuitry comprising: an address table to store memory addresses for which a data element accessed by the processing element resulted in a cache miss or an access to a previously prefetched data element; and detector circuitry to detect, for each of a group of candidate offset values, one or more respective metrics representing a proportion of a set of data element accesses which resulted in a cache miss or an access to a previously prefetched data element, for which the memory address for that data element access differs by the candidate offset value from a memory address in the address table; in which the detector circuitry is configured to process the group of candidate offset values as successive complementary sub-groups of one or more of the group of candidate offset values and to set a next instance of the current offset value in response to processing each sub-group, in dependence upon the proportions indicated by the one or more detected metrics for that sub-group; and the one or more metrics previously detected for the current offset value.

公开(公告)号：US10430192B2

公开(公告)日：2019-10-01

申请号：US15748734

申请日：2016-07-28

Applicant: ARM LIMITED

Inventor： Nigel John Stephens ,  Grigorios Magklis ,  Alejandro Martinez Vicente ,  Nathanael Premillieu ,  Mbou Eyole

IPC: G06F9/30 ,  G06F9/38

Abstract: Data processing apparatus comprises processing circuitry to selectively apply vector processing operations to one or more data items of a data vector comprising a plurality of data items at respective positions in the data vector, according to the state of respective predicate flags associated with the positions; the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry; wherein the instruction decoder circuitry is responsive to a WHILE instruction and a CHANGE instruction, to control the instruction processing dependent upon a number of the predicate flags.