公开(公告)号：US10990727B1

公开(公告)日：2021-04-27

申请号：US17016816

申请日：2020-09-10

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Brian A. Saari ,  Stephen A. Chadwick ,  Jason T. Dowling ,  Michael J. Frack ,  David D. Moser ,  Mark R. Shaffer

IPC: G06F30/33 ,  G06F30/343 ,  G06F30/3308 ,  G06F30/337 ,  G06F30/398 ,  G06F30/333

Abstract: An IC design enhancing tool for automatically reviewing and environmentally hardening an IC design layout. The IC design enhancing tool may be realized, for example, in software that scans through an IC netlist generated by an electronic design automation (EDA) tool and replaces components that are not compliant with one or more hardening criteria. The newly created netlist can then be re-checked by the EDA tool and an iterative process takes place between the EDA tool and the IC design enhancing tool until the final design layout is fully compliant for a given environment. Interrogation of the IC design layout involves determining if at least a portion of the hardware layout netlist meets one or more predetermined hardening criteria. If it does not, then one or more of the hardware components are replaced using one or more predefined hardened components.