公开(公告)号：US10990727B1

公开(公告)日：2021-04-27

申请号：US17016816

申请日：2020-09-10

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Brian A. Saari ,  Stephen A. Chadwick ,  Jason T. Dowling ,  Michael J. Frack ,  David D. Moser ,  Mark R. Shaffer

IPC: G06F30/33 ,  G06F30/343 ,  G06F30/3308 ,  G06F30/337 ,  G06F30/398 ,  G06F30/333

Abstract: An IC design enhancing tool for automatically reviewing and environmentally hardening an IC design layout. The IC design enhancing tool may be realized, for example, in software that scans through an IC netlist generated by an electronic design automation (EDA) tool and replaces components that are not compliant with one or more hardening criteria. The newly created netlist can then be re-checked by the EDA tool and an iterative process takes place between the EDA tool and the IC design enhancing tool until the final design layout is fully compliant for a given environment. Interrogation of the IC design layout involves determining if at least a portion of the hardware layout netlist meets one or more predetermined hardening criteria. If it does not, then one or more of the hardware components are replaced using one or more predefined hardened components.

公开(公告)号：US11108383B1

公开(公告)日：2021-08-31

申请号：US17025049

申请日：2020-09-18

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： David D. Moser ,  Michael J. Frack ,  Mark R. Shaffer ,  Daniel L. Stanley

IPC: H03K5/13 ,  H03K5/01 ,  H03K19/21 ,  G06F1/06 ,  G06F1/08 ,  G11C19/28 ,  H03K5/00

Abstract: A clock phase control circuit includes a clock input gate module, first and second shift register divider modules, and a multiplexer. The clock input gate module is configured to produce, based on an oscillating input clock signal, first and second intermediate clock signals. The first shift register divider module is configured to produce at least one first phase clock signal based on the first intermediate clock signal, where the at least one first phase clock signal has a different frequency than the first intermediate clock signal. The second shift register divider module is configured to produce at least one second phase clock signal based on the second intermediate clock signal, where the at least one second phase clock signal has a different frequency than the second intermediate clock signal. The multiplexer is configured to produce an output clock signal by selecting one of the first or second phase clock signals.