公开(公告)号：US20150171846A1

公开(公告)日：2015-06-18

申请号：US14631982

申请日：2015-02-26

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Robert Ensinger ,  David M. Gillespie

IPC: H03K5/1252

CPC classification number: H03K5/1252 ,  G06F1/02 ,  G06F1/10

Abstract: Techniques and architecture are disclosed for improving spurious performance in a signal generator/system. The disclosed techniques/architecture can be used, for example, to enhance/improve the wideband and/or narrowband spurious free dynamic range (SFDR) between a given carrier signal and spurious signals. In some example instances, wideband and/or narrowband SFDR may be improved to about −40 dBc or better. In some other example instances, wideband and/or narrowband SFDR may be improved to about −70 dBc or better. The disclosed techniques/architecture can be implemented in a wide variety of signal generators/systems, such as a direct digital synthesizer (DDS)-based system, and over a wide range of input clock frequencies (e.g., in the range of about 10 MHz to 40 GHz, or higher).

Abstract translation: 公开了用于改善信号发生器/系统中的假性能的技术和架构。 所公开的技术/架构可以用于例如增强/改善给定载波信号和杂散信号之间的宽带和/或窄带无杂散动态范围（SFDR）。 在一些示例中，宽带和/或窄带SFDR可以提高到大约-40dBc或更好。 在一些其他示例性实例中，宽带和/或窄带SFDR可以提高到大约-70dBc或更好。 公开的技术/架构可以在各种各样的信号发生器/系统中实现，例如基于直接数字合成器（DDS）的系统，以及在宽范围的输入时钟频率（例如，在约10MHz的范围内） 至40GHz或更高）。

公开(公告)号：US09461636B2

公开(公告)日：2016-10-04

申请号：US14631982

申请日：2015-02-26

Applicant: BAE Systems Information and Electronic Systems Integration Inc.

Inventor： Robert Ensinger ,  David M. Gillespie

IPC: H03K21/00 ,  H03K5/1252 ,  G06F1/10

CPC classification number: H03K5/1252 ,  G06F1/02 ,  G06F1/10

Abstract: Techniques and architecture are disclosed for improving spurious performance in a signal generator/system. The disclosed techniques/architecture can be used, for example, to enhance/improve the wideband and/or narrowband spurious free dynamic range (SFDR) between a given carrier signal and spurious signals. In some example instances, wideband and/or narrowband SFDR may be improved to about −40 dBc or better. In some other example instances, wideband and/or narrowband SFDR may be improved to about −70 dBc or better. The disclosed techniques/architecture can be implemented in a wide variety of signal generators/systems, such as a direct digital synthesizer (DDS)-based system, and over a wide range of input clock frequencies (e.g., in the range of about 10 MHz to 40 GHz, or higher).