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公开(公告)号：US12135849B2
公开(公告)日：2024-11-05
申请号：US17789243
申请日：2021-08-04
Inventor： Peng Liu , Peirong Huo , Hong Liu , Chao Liang , Aiyu Ding , Zhenhong Xiao , Yongqiang Zhang , Yusheng Liu , Jingyi Xu , Jiantao Liu , Bo Li
IPC: G06F3/041
Abstract: Provided is a touch display substrate. The touch display substrate includes a base substrate, including a display region and a non-display region; a plurality of touch electrodes disposed in the display region; and a plurality of signal transmission circuits, a plurality of first control lines, a plurality of second control lines, a target signal line, and a plurality of touch signal lines that are disposed in the non-display region.
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公开(公告)号：US12111554B2
公开(公告)日：2024-10-08
申请号：US17791338
申请日：2021-08-18
Inventor： Hong Liu , Jingyi Xu , Xiaochun Xu , Jiantao Liu , Wanzhi Chen , Chengfu Xu , Bo Li , Yongqiang Zhang , Peng Liu , Ruirui Hao , Yu Feng , Xinguo Wu
IPC: G02F1/1368 , H10K59/124
CPC classification number: G02F1/1368 , H10K59/124
Abstract: The present disclosure provides a display substrate and a display panel, and belongs to the field of display technology. The present display substrate includes a display region and a peripheral region surrounding the display region; the display substrate includes: a base substrate; a plurality of insulating layers sequentially arranged along a direction away from the base substrate; wherein each of the plurality of insulating layers is located in the display region and the peripheral region; one or more protrusion structures arranged between at least two adjacent ones of the plurality of insulating layers and in the peripheral region.
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公开(公告)号：US10672491B2
公开(公告)日：2020-06-02
申请号：US15770798
申请日：2017-11-03
Inventor： Xianrui Qian , Bo Li
Abstract: A shift register, an array substrate and a display device in the field of display technology are provided in the present disclosure. In the shift register, the gate electrode of the first transistor is connected to a second node, one of the source electrode and the drain electrode is connected to a first clock signal line, and the other one is connected to the first node. The gate electrode of the second transistor is connected to the second node, one of the source electrode and the drain electrode is connected to the second node, and the other one is connected to the first clock signal line. The charging circuitry is configured to set the second node to an effective level when a second clock signal line is at an effective level. The memory circuitry is configured to store the threshold voltage of the second transistor and compensate the threshold voltage of the first transistor with the stored threshold voltage.
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公开(公告)号：US20190172392A1
公开(公告)日：2019-06-06
申请号：US16152263
申请日：2018-10-04
Inventor： Xianrui Qian , Yuting Chen , Zixuan Wang , Bo Li , Fei Li
IPC: G09G3/3233
Abstract: The present disclosure relates to a pixel driving circuit and a driving method for the same and a display panel. The pixel driving circuit includes a driver unit, a circuit switching unit, and a storage capacitor unit. The driver unit includes a first sub-driver unit and a second sub-driver unit. The circuit switching unit has a first switching unit and a second switching unit. Two terminals of the first switching unit are electrically connected to a first terminal of the light emitting unit and the first sub-driver unit, respectively, two terminals of the second switching unit are electrically connected to the light emitting unit and the second sub-driver unit, respectively, and the circuit switching unit is configured to switch conductive states of the first switching unit and the second switching unit.
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5.发明申请公开(公告)号：US20190156752A1
公开(公告)日：2019-05-23
申请号：US16091272
申请日：2018-02-27
Inventor： Xianrui Qian , Bo Li , Yunlong Cai
IPC: G09G3/3258
Abstract: The invention discloses a pixel driving circuit, a driving method, an organic light emitting display panel and a display device. The pixel driving circuit comprises a data writing module (1), a memory module (2), at least one first light emitting device (D1), a first driving module (3) which corresponds to the various first light emitting devices (D1) one by one, at least one second light emitting device (D2) and a second driving module (4) which corresponds to the various second light emitting devices (D2) one by one. Through mutual cooperation of each module, the voltage of a node can be switched between a positive value and a negative value by virtue of a simple structure, so that performances of the first driving module (3) and the second driving module (4) are recovered, and then the influence on the stability and the service life of the display panel due to performance offset of the first driving module (3) and the second driving module (4) is relieved.
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Patent Agency Ranking
公开(公告)号：US12259623B2
公开(公告)日：2025-03-25
申请号：US18028523
申请日：2022-03-31
Inventor： Peirong Huo , Chao Liang , Peng Liu , Jingyi Xu , Bo Li , Zhenhong Xiao
IPC: G02F1/1362
Abstract: An includes a display area and a non-display area that at least partially surrounds the display area; the non-display area includes at least two clock signal lines, wherein a ratio of a spacing between two adjacent clock signal lines to a line width of the clock signal lines is greater than or equal to 3.
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公开(公告)号：US11367469B2
公开(公告)日：2022-06-21
申请号：US15766937
申请日：2017-10-09
Inventor： Xianrui Qian , Guolei Wang , Tong Yang , Suzhen Mu , Peng Chen , Yuting Chen , Zixuan Wang , Bo Li
Abstract: A shift register unit circuit includes an input sub-circuit, a pull-up sub-circuit, a pull-down control sub-circuit, a pull-down sub-circuit, and a voltage regulating sub-circuit. The input sub-circuit receives an input signal from a signal input terminal to control a potential of a pull-up node. The pull-up sub-circuit outputs a gate driving signal to an output terminal under control of the potential of the pull-up node and a signal from a first signal terminal. The pull-down control sub-circuit conducts a pull-down node with a first node under control of a signal from the second signal terminal. The pull-down sub-circuit conducts the pull-up node with the first node and the turn-down signal terminal with the output terminal under control of a potential of the pull-down node. The voltage regulating sub-circuit conducts the first node with the turn-down signal terminal under control of a potential of the first node.
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公开(公告)号：US11328663B2
公开(公告)日：2022-05-10
申请号：US16339565
申请日：2018-09-28
Inventor： Xianrui Qian , Fei Li , Bo Li , Yuting Chen , Zixuan Wang
IPC: G09G3/3233
Abstract: The present disclosure provides a pixel driving circuit, a driving method thereof, and a display device, and relates to the field of display technology. The pixel driving circuit includes a first driver, a second driver, and a light emitting element. The first driver is configured to generate a first driving current. The second driver is configured to generate a second driving current. The first driving current and the second driving current alternately drive the light emitting element as a main driving current.
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公开(公告)号：US20220137471A1
公开(公告)日：2022-05-05
申请号：US17342604
申请日：2021-06-09
Inventor： Yongqiang Zhang , Jingyi Xu , Hong Liu , Peng Liu , Peirong Huo , Aiyu Ding , Zhenhong Xiao , Bo Li , Bo Huang
IPC: G02F1/1362
Abstract: A substrate in an array substrate includes a light aperture region and a winding region arranged around the light aperture region. On the substrate, an orthographic projection of a first winding in each first signal line is overlapped with an orthographic projection of a second winding in a corresponding second signal line. In this way, the distance between two adjacent signal lines in the winding region is larger, and the parasitic capacitance generated between them is smaller.
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公开(公告)号：US11222567B2
公开(公告)日：2022-01-11
申请号：US16334938
申请日：2018-08-14
Inventor： Xianrui Qian , Zixuan Wang , Yuting Chen , Fei Li , Bo Li
Abstract: A shift register circuit includes a noise reduction sub-circuit and a pull-down node control sub-circuit. A control end of the noise reduction sub-circuit is connected to a pull-down node, the noise reduction sub-circuit is connected to a first voltage input end. The pull-down node control sub-circuit includes a first pull-down node control sub-circuit and a second pull-down node control sub-circuit. The second pull-down node control sub-circuit controls the pull-down control node to be connected to a first clock signal input end when the first clock signal input end inputs a first level, the pull-down node to be connected to the first clock signal input end when a potential of the pull-down control node is at the first level, so that the potential of the pull-down node is at a first level and a noise reduction transistor included in the noise reduction sub-circuit is turned off.
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