公开(公告)号：US5390298A

公开(公告)日：1995-02-14

申请号：US183217

申请日：1994-01-14

申请人： Bradley C. Kuszmaul ,  Charles E. Leiserson ,  Shaw-Wen Yang ,  Carl R. Feynman ,  W. Daniel Hillis ,  David Wells ,  Cynthia J. Spiller

发明人： Bradley C. Kuszmaul ,  Charles E. Leiserson ,  Shaw-Wen Yang ,  Carl R. Feynman ,  W. Daniel Hillis ,  David Wells ,  Cynthia J. Spiller

IPC分类号： G06F15/16 ,  G06F11/00 ,  G06F11/08 ,  G06F11/22 ,  G06F15/173 ,  G06F15/80 ,  G06F13/00

CPC分类号： G06F15/17381 ,  G06F11/08 ,  G06F11/22 ,  G06F11/324 ,  G06F15/17343 ,  H04L45/48 ,  H04L49/35 ,  H04L49/555 ,  G06F2201/88

摘要： A computer including a processor array and a routing network. Processors in the processor array generate messages for transfer to over the routing network, each message including a path identifier portion identifying a path from a source, message processor to a destination processor. The routing network comprises a plurality of interconnected router nodes, at least some of said router nodes being connected to the processors to receive messages therefrom and transmit messages thereto. Each router node operates in a plurality of modes. In a first mode, the router nodes couple received messages to a router node connected thereto in accordance with the path identifier portion to thereby transfer each respective message along the path identified in its path identifier portion. In a second mode, the router node couple received messages to predetermined ones of the router nodes or processors connected thereto, the predetermined ones of said router nodes or processors being selected to facilitate transfer of a message to a nearby processor to facilitate the rapid emptying of the routing network of messages. A control element controls the router nodes to enable them to operate in the first mode or second mode generally contemporaneously.

摘要翻译： 包括处理器阵列和路由网络的计算机。 处理器阵列中的处理器产生用于通过路由网络传送的消息，每个消息包括标识从源，消息处理器到目的地处理器的路径的路径标识符部分。 路由网络包括多个互连的路由器节点，所述路由器节点中的至少一些连接到处理器以从其接收消息并向其发送消息。 每个路由器节点以多种模式操作。 在第一模式中，路由器节点根据路径标识符部分将接收到的消息耦合到与其连接的路由器节点，从而沿着其路径标识符部分中标识的路径传送每个相应的消息。 在第二模式中，路由器节点将接收到的消息耦合到连接到其上的路由器节点或处理器中的预定路由器节点，所选择的所述路由器节点或处理器中的预定路由器节点或处理器便于将消息传送到附近的处理器，以便于快速排空 消息的路由网络。 控制元件控制路由器节点，使得它们能够在第一模式或第二模式下同时运行。

公开(公告)号：US6047122A

公开(公告)日：2000-04-04

申请号：US916136

申请日：1997-08-21

申请人： Cynthia J. Spiller

发明人： Cynthia J. Spiller

IPC分类号： G06F9/48 ,  G06F13/00

CPC分类号： G06F9/4843

摘要： A parallel computer comprises a plurality of processing elements and a control processor all interconnected by a communications network. The control processor and the processing elements process a plurality of user programs, with the control processor and the processing elements processing each user program in parallel. The control processor, while processing each user program, generates user program processing commands and transfers them to the processing elements over the communications network, and each the processing element processes data associated with a particular user program in response to each user program processing command received from the communications network. The control processor periodically further generates a context switch command to enable the processing elements to, in parallel, perform a context switch operation, in which they switch processing of a user program they are currently processing and begin processing of another user program.

摘要翻译： 并行计算机包括多个处理元件和全部由通信网络互连的控制处理器。 控制处理器和处理元件处理多个用户程序，其中控制处理器和处理元件并行地处理每个用户程序。 控制处理器在处理每个用户程序时产生用户程序处理命令并通过通信网络将它们传送到处理元件，并且每个处理元件响应于从用户程序处理命令接收到的每个用户程序处理命令处理与特定用户程序相关联的数据 通信网络。 控制处理器周期性地进一步产生上下文切换命令，使得处理元件能够并行执行上下文切换操作，在该切换操作中，它们切换其当前正在处理的用户程序的处理，并开始处理其他用户程序。