公开(公告)号：US5390298A

公开(公告)日：1995-02-14

申请号：US183217

申请日：1994-01-14

申请人： Bradley C. Kuszmaul ,  Charles E. Leiserson ,  Shaw-Wen Yang ,  Carl R. Feynman ,  W. Daniel Hillis ,  David Wells ,  Cynthia J. Spiller

发明人： Bradley C. Kuszmaul ,  Charles E. Leiserson ,  Shaw-Wen Yang ,  Carl R. Feynman ,  W. Daniel Hillis ,  David Wells ,  Cynthia J. Spiller

IPC分类号： G06F15/16 ,  G06F11/00 ,  G06F11/08 ,  G06F11/22 ,  G06F15/173 ,  G06F15/80 ,  G06F13/00

CPC分类号： G06F15/17381 ,  G06F11/08 ,  G06F11/22 ,  G06F11/324 ,  G06F15/17343 ,  H04L45/48 ,  H04L49/35 ,  H04L49/555 ,  G06F2201/88

摘要： A computer including a processor array and a routing network. Processors in the processor array generate messages for transfer to over the routing network, each message including a path identifier portion identifying a path from a source, message processor to a destination processor. The routing network comprises a plurality of interconnected router nodes, at least some of said router nodes being connected to the processors to receive messages therefrom and transmit messages thereto. Each router node operates in a plurality of modes. In a first mode, the router nodes couple received messages to a router node connected thereto in accordance with the path identifier portion to thereby transfer each respective message along the path identified in its path identifier portion. In a second mode, the router node couple received messages to predetermined ones of the router nodes or processors connected thereto, the predetermined ones of said router nodes or processors being selected to facilitate transfer of a message to a nearby processor to facilitate the rapid emptying of the routing network of messages. A control element controls the router nodes to enable them to operate in the first mode or second mode generally contemporaneously.

摘要翻译： 包括处理器阵列和路由网络的计算机。 处理器阵列中的处理器产生用于通过路由网络传送的消息，每个消息包括标识从源，消息处理器到目的地处理器的路径的路径标识符部分。 路由网络包括多个互连的路由器节点，所述路由器节点中的至少一些连接到处理器以从其接收消息并向其发送消息。 每个路由器节点以多种模式操作。 在第一模式中，路由器节点根据路径标识符部分将接收到的消息耦合到与其连接的路由器节点，从而沿着其路径标识符部分中标识的路径传送每个相应的消息。 在第二模式中，路由器节点将接收到的消息耦合到连接到其上的路由器节点或处理器中的预定路由器节点，所选择的所述路由器节点或处理器中的预定路由器节点或处理器便于将消息传送到附近的处理器，以便于快速排空 消息的路由网络。 控制元件控制路由器节点，使得它们能够在第一模式或第二模式下同时运行。

公开(公告)号：US5530809A

公开(公告)日：1996-06-25

申请号：US181711

申请日：1994-01-14

申请人： David C. Douglas ,  Charles E. Leiserson ,  Bradley C. Kuszmaul ,  Shaw-Wen Yang ,  W. Daniel Hillis ,  David Wells ,  Carl R. Feynman ,  Bruce J. Walker ,  Brewster Kahle

发明人： David C. Douglas ,  Charles E. Leiserson ,  Bradley C. Kuszmaul ,  Shaw-Wen Yang ,  W. Daniel Hillis ,  David Wells ,  Carl R. Feynman ,  Bruce J. Walker ,  Brewster Kahle

IPC分类号： G06F15/16 ,  G06F11/00 ,  G06F11/08 ,  G06F11/22 ,  G06F15/173 ,  G06F15/80 ,  G06F15/163

CPC分类号： G06F15/17381 ,  G06F11/08 ,  G06F11/22 ,  G06F11/324 ,  G06F15/17343 ,  H04L45/48 ,  H04L49/35 ,  H04L49/555 ,  G06F2201/88

摘要： A digital computer comprising a plurality of message generating nodes interconnected by a routing network. The routing network transfers messages among the message generating elements in accordance with address information identifying a destination message generating element. Each message generating node includes a message data generator and a network interface. The message data generator generates message data items each including an address data portion comprising a destination identifier. The network interface includes a message generator and an address translation table, the table including a plurality of entries identifying, for at least one destination identifier, a translated destination identifier. The message generator, in response to the receipt of a message data item from the message data generator, generates a message for transmission to the routing network. In generating the message, the message generator performs an address translation operation in connection with the address data and the contents of the address translation table to generate updated address data which it uses data in connection with generating address information for the message.

摘要翻译： 一种数字计算机，包括由路由网络互连的多个消息生成节点。 路由网络根据识别目的地消息生成元素的地址信息在消息生成元件之间传送消息。 每个消息生成节点包括消息数据生成器和网络接口。 消息数据生成器生成包括包括目的地标识符的地址数据部分的消息数据项。 网络接口包括消息发生器和地址转换表，该表包括多个条目，用于为至少一个目的地标识符标识已翻译的目的地标识符。 消息生成器响应于从消息数据生成器接收到消息数据项，生成用于传输到路由网络的消息。 在生成消息时，消息生成器执行与地址数据和地址转换表的内容相关的地址转换操作，以生成更新的地址数据，其使用与为消息生成地址信息相结合的数据。

公开(公告)号：US5680550A

公开(公告)日：1997-10-21

申请号：US388031

申请日：1995-02-13

申请人： Bradley C. Kuszmaul ,  Charles E. Leiserson ,  Shaw-Wen Yang ,  Carl R. Feynman ,  W. Daniel Hillis ,  David C. Douglas

发明人： Bradley C. Kuszmaul ,  Charles E. Leiserson ,  Shaw-Wen Yang ,  Carl R. Feynman ,  W. Daniel Hillis ,  David C. Douglas

IPC分类号： G06F15/16 ,  G06F11/00 ,  G06F11/08 ,  G06F11/22 ,  G06F15/173 ,  G06F15/80 ,  G06F13/00 ,  G06F3/00

CPC分类号： G06F15/17381 ,  G06F11/08 ,  G06F11/22 ,  G06F11/324 ,  G06F15/17343 ,  H04L45/48 ,  H04L49/35 ,  H04L49/555 ,  G06F2201/88

摘要： A digital computer includes a plurality of processing elements, a command processor, a diagnostic processor and a communications network. The processing elements each performs data processing and data communications operations in connection with commands. The processing elements also performing diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The command processor generates commands for the processing elements, and also performs diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The diagnostic processor generates diagnostic requests. The communication network includes three elements, including a data router, a control network and a diagnostic network. The data router is connected to the processing elements for facilitating the transfer of data among them during a data communications operation. The control network is connected to the processing elements and the command processor for transferring commands from the command processor to the processing elements. The diagnostic network connected to the processing elements, the command processor and the diagnostic processor for transferring diagnostic requests from the diagnostic processor to the processing elements and the command processor and for transferring diagnostic results from the processing elements and the command processor to the diagnostic processor.

摘要翻译： 数字计算机包括多个处理元件，命令处理器，诊断处理器和通信网络。 处理元件各自执行与命令相关的数据处理和数据通信操作。 处理元件还响应诊断操作请求执行诊断操作，并响应于此提供诊断结果。 命令处理器为处理元件生成命令，并且还响应诊断操作请求执行诊断操作并响应于此提供诊断结果。 诊断处理器产生诊断请求。 通信网络包括三个元件，包括数据路由器，控制网络和诊断网络。 数据路由器连接到处理元件，以便在数据通信操作期间便于它们之间的数据传输。 控制网络连接到处理元件和命令处理器，用于将命令从命令处理器传送到处理元件。 连接到处理元件的诊断网络，命令处理器和诊断处理器，用于将诊断请求从诊断处理器传送到处理元件和命令处理器，并将诊断结果从处理元件和命令处理器传送到诊断处理器。

公开(公告)号：US5333268A

公开(公告)日：1994-07-26

申请号：US946242

申请日：1992-09-16

申请人： David C. Douglas ,  Mahesh N. Ganmukhi ,  Jeffrey V. Hill ,  W. Daniel Hillis ,  Bradley C. Kuszmaul ,  Charles E. Leiserson ,  David S. Wells ,  Monica C. Wong ,  Shaw-Wen Yang ,  Robert C. Zak

发明人： David C. Douglas ,  Mahesh N. Ganmukhi ,  Jeffrey V. Hill ,  W. Daniel Hillis ,  Bradley C. Kuszmaul ,  Charles E. Leiserson ,  David S. Wells ,  Monica C. Wong ,  Shaw-Wen Yang ,  Robert C. Zak

IPC分类号： G06F15/16 ,  G06F11/00 ,  G06F11/08 ,  G06F11/22 ,  G06F15/173 ,  G06F15/80

CPC分类号： G06F15/17381 ,  G06F11/08 ,  G06F11/22 ,  G06F11/324 ,  G06F15/17343 ,  H04L45/48 ,  H04L49/35 ,  H04L49/555 ,  G06F2201/88

摘要： A digital computer includes a plurality of processing elements, a command processor, a diagnostic processor and a communications network. The processing elements each performs data processing and data communications operations in connection with commands. The processing elements also performing diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The command processor generates commands for the processing elements, and also performs diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The diagnostic processor generates diagnostic requests. The communication network includes three elements, including a data router, a control network and a diagnostic network. The data router is connected to the processing elements for facilitating the transfer of data among them during a data communications operation. The control network is connected to the processing elements and the command processor for transferring commands from the command processor to the processing elements. The diagnostic network connected to the processing elements, the command processor and the diagnostic processor for transferring diagnostic requests from the diagnostic processor to the processing elements and the command processor and for transferring diagnostic results from the processing elements and the command processor to the diagnostic processor.

摘要翻译： 数字计算机包括多个处理元件，命令处理器，诊断处理器和通信网络。 处理元件各自执行与命令相关的数据处理和数据通信操作。 处理元件还响应诊断操作请求执行诊断操作，并响应于此提供诊断结果。 命令处理器为处理元件生成命令，并且还响应诊断操作请求执行诊断操作并响应于此提供诊断结果。 诊断处理器产生诊断请求。 通信网络包括三个元件，包括数据路由器，控制网络和诊断网络。 数据路由器连接到处理元件，以便在数据通信操作期间便于它们之间的数据传输。 控制网络连接到处理元件和命令处理器，用于将命令从命令处理器传送到处理元件。 连接到处理元件的诊断网络，命令处理器和诊断处理器，用于将诊断请求从诊断处理器传送到处理元件和命令处理器，并将诊断结果从处理元件和命令处理器传送到诊断处理器。

公开(公告)号：US5590283A

公开(公告)日：1996-12-31

申请号：US380854

申请日：1995-01-27

申请人： W. Daniel Hillis ,  David C. Douglas ,  Charles E. Leiserson ,  Bradley C. Kuszmaul ,  Mahesh N. Ganmukhi ,  Jeffrey V. Hill ,  Monica C. Wong-Chan

发明人： W. Daniel Hillis ,  David C. Douglas ,  Charles E. Leiserson ,  Bradley C. Kuszmaul ,  Mahesh N. Ganmukhi ,  Jeffrey V. Hill ,  Monica C. Wong-Chan

IPC分类号： G06F15/16 ,  G06F11/00 ,  G06F11/08 ,  G06F11/22 ,  G06F15/173 ,  G06F15/80 ,  G06F15/163

CPC分类号： G06F15/17381 ,  G06F11/08 ,  G06F11/22 ,  G06F11/324 ,  G06F15/17343 ,  H04L45/48 ,  H04L49/35 ,  H04L49/555 ,  G06F2201/88

摘要： A digital computer comprises a plurality of processing elements, a communications router, and a control network. Each processing element performs data processing operations in connection with commands, at least some of the processing elements performing the data processing operations in connection with the commands in messages they receive over the control network. Each processing element also generates and receives data transfer messages, each including an address portion containing an address, for transfer to another processing element as identified by the address. At least one of the processing elements further generates the control network messages for transfer over the communications router. The communications router comprises router nodes interconnected in the form of a "fat-tree," and the control network comprises control network nodes interconnected in the form of a tree, with the processing elements being connected at the leaf nodes of the respective communications router and control network.

摘要翻译： 数字计算机包括多个处理元件，通信路由器和控制网络。 每个处理单元执行与命令有关的数据处理操作，至少一些处理单元通过控制网络接收的消息中的命令进行数据处理操作。 每个处理元件还产生和接收数据传送消息，每个数据传送消息包括包含地址的地址部分，用于传送到由该地址识别的另一个处理元件。 处理元件中的至少一个进一步生成用于通过通信路由器传送的控制网络消息。 通信路由器包括以“胖树”形式互连的路由器节点，并且控制网络包括以树形式互连的控制网络节点，处理元件连接在相应通信路由器的叶节点处， 控制网络。

公开(公告)号：US5388214A

公开(公告)日：1995-02-07

申请号：US183219

申请日：1994-01-14

申请人： Charles E. Leiserson ,  Robert C. Zak, Jr. ,  W. Daniel Hillis ,  Bradley C. Kuszmaul ,  Jeffrey V. Hill

发明人： Charles E. Leiserson ,  Robert C. Zak, Jr. ,  W. Daniel Hillis ,  Bradley C. Kuszmaul ,  Jeffrey V. Hill

IPC分类号： G06F15/16 ,  G06F11/00 ,  G06F11/08 ,  G06F11/22 ,  G06F15/173 ,  G06F15/80 ,  G06F13/00

CPC分类号： G06F15/17381 ,  G06F11/08 ,  G06F11/22 ,  G06F11/324 ,  G06F15/17343 ,  H04L45/48 ,  H04L49/35 ,  H04L49/555 ,  G06F2201/88

摘要： A computer comprising a plurality of processing nodes, a control node and a request distribution network. Each processing node receives processing requests and generates in response processed data. The control node generates processing requests for transfer to selected ones of the processing nodes as identified by associated request address information, and receives processed data in response, the request address information identifying selected ones of the processing nodes to receive a processing request in parallel. The request distribution network distributes the processing requests to the processing nodes and returns processed data to the control node. The network includes a plurality of request distribution nodes connected in a plurality of levels to form a tree-structure, including an upper root level and a lower leaf level. Each request distribution node is connected to receive processing requests from, and to couple processed data to, a parent, the parent of the request distribution node of the root level comprising the control node, and each request distribution node being further connected to couple processing requests to and receive processed data from, selected children, the children of the request distribution nodes of the leaf level comprising the processing nodes. Each request distribution node, in response to request address information received from its parent, identifies selected ones of its children and thereafter couples further request address information which it receives and processing requests in parallel to its children.

摘要翻译： 一种包括多个处理节点，控制节点和请求分发网络的计算机。 每个处理节点接收处理请求并响应处理的数据生成。 控制节点生成用于传送到由相关联的请求地址信息识别的所选处理节点的处理请求，并响应于接收处理的数据，请求地址信息识别处理节点中选择的一个并行接收处理请求。 请求分配网络将处理请求分配给处理节点，并将处理后的数据返回给控制节点。 网络包括以多个级别连接的多个请求分发节点，以形成包括上根级和下叶级的树结构。 每个请求分发节点被连接以接收处理的请求，并且将处理的数据耦合到父节点，包括控制节点的根级别的请求分发节点的父节点，并且每个请求分配节点进一步连接以耦合处理请求 从所选择的孩子接收和接收包括处理节点的叶级别的请求分发节点的子节点。 每个请求分发节点响应于从其父节点接收到的请求地址信息，识别其子节点中的所选择的一个，然后将其接收到的进一步的请求地址信息与其子节点并行处理请求。

公开(公告)号：US5118975A

公开(公告)日：1992-06-02

申请号：US489079

申请日：1990-03-05

申请人： W. Daniel Hillis ,  Zahi S. Abuhamdeh ,  Bradley C. Kuszmaul ,  Jon P. Wade ,  Shaw-Wen Yang

发明人： W. Daniel Hillis ,  Zahi S. Abuhamdeh ,  Bradley C. Kuszmaul ,  Jon P. Wade ,  Shaw-Wen Yang

IPC分类号： H03K5/135 ,  G06F1/10 ,  G11C11/407 ,  H03L7/00 ,  H03L7/081 ,  H03L7/087 ,  H03L7/089

CPC分类号： G06F1/10 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/089

摘要： A clock buffer circuit that generates a local clock signal in response to a system clock signal. The clock buffer circuit includes a buffer circuit for generating the local clock signal in response to an intermediate clock signal. A buffer control circuit generates the intermediate clock signal in response to the system clock signal and the local clock signal. The buffer control circuit provides a variable delay so that, with an additional delay provided by the buffer circuit, the local clock signal has a selected phase relationship in relation to the system clock signal.

公开(公告)号：US07925839B1

公开(公告)日：2011-04-12

申请号：US12168689

申请日：2008-07-07

申请人： Steven C. Miller ,  Martin M. Deneroff ,  Curt F. Schimmel ,  Larry Rudolph ,  Charles E. Leiserson ,  Bradley C. Kuszmaul ,  Krste Asanovic

发明人： Steven C. Miller ,  Martin M. Deneroff ,  Curt F. Schimmel ,  Larry Rudolph ,  Charles E. Leiserson ,  Bradley C. Kuszmaul ,  Krste Asanovic

IPC分类号： G06F12/00

CPC分类号： G06F12/0815 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0831

摘要： A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.

摘要翻译： 处理器可以以多个操作状态中的一个操作。 在正常操作状态下，处理器不涉及存储器事务。 在接收到访问存储器位置的事务指令时，处理器转换到事务操作状态。 在事务操作状态中，处理器执行对高速缓存线的更改和与存储器位置相关联的数据。 在事务操作状态下，数据和高速缓存行的任何更改对于计算系统中的其他处理器是不可见的。 响应于接收到提交指令，处理器进入提交操作状态时，这些更改变为可见。 更改变为可见后，处理器返回到正常运行状态。 如果在接收提交指令之前发生中止事件，则处理器转换到中止操作状态，其中对数据和高速缓存行的任何改变被丢弃。

公开(公告)号：US07398359B1

公开(公告)日：2008-07-08

申请号：US10836932

申请日：2004-04-30

申请人： Steven C. Miller ,  Martin M. Deneroff ,  Curt F. Schimmel ,  Larry Rudolph ,  Charles E. Leiserson ,  Bradley C. Kuszmaul ,  Krste Asanovic

发明人： Steven C. Miller ,  Martin M. Deneroff ,  Curt F. Schimmel ,  Larry Rudolph ,  Charles E. Leiserson ,  Bradley C. Kuszmaul ,  Krste Asanovic

IPC分类号： G06F12/00

CPC分类号： G06F12/0815 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0831

摘要： A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.

摘要翻译： 处理器可以以多个操作状态中的一个操作。 在正常操作状态下，处理器不涉及存储器事务。 在接收到访问存储器位置的事务指令时，处理器转换到事务操作状态。 在事务操作状态下，处理器执行对高速缓存行的更改和与存储器位置相关联的数据。 在事务操作状态下，数据和高速缓存行的任何更改对于计算系统中的其他处理器是不可见的。 响应于接收到提交指令，处理器进入提交操作状态时，这些更改变得可见。 更改变为可见后，处理器返回到正常运行状态。 如果在接收提交指令之前发生中止事件，则处理器转换到中止操作状态，其中对数据和高速缓存行的任何改变被丢弃。

公开(公告)号：US20110191545A1

公开(公告)日：2011-08-04

申请号：US13084280

申请日：2011-04-11

申请人： Steven C. Miller ,  Martin M. Deneroff ,  Curt F. Schimmel ,  Larry Rudolph ,  Charles E. Leiserson ,  Bradley C. Kuszmaul ,  Krste Asanovic

发明人： Steven C. Miller ,  Martin M. Deneroff ,  Curt F. Schimmel ,  Larry Rudolph ,  Charles E. Leiserson ,  Bradley C. Kuszmaul ,  Krste Asanovic

IPC分类号： G06F12/08

CPC分类号： G06F12/0815 ,  G06F9/3004 ,  G06F9/30087 ,  G06F12/0831

摘要： A processor may operate in one of a plurality of operating states. In a Normal operating state, the processor is not involved with a memory transaction. Upon receipt of a transaction instruction to access a memory location, the processor transitions to a Transaction operating state. In the Transaction operating state, the processor performs changes to a cache line and data associated with the memory location. While in the Transaction operating state, any changes to the data and the cache line is not visible to other processors in the computing system. These changes become visible upon the processor entering a Commit operating state in response to receipt of a commit instruction. After changes become visible, the processor returns to the Normal operating state. If an abort event occurs prior to receipt of the commit instruction, the processor transitions to an Abort operating state where any changes to the data and cache line are discarded.

摘要翻译： 处理器可以以多个操作状态中的一个操作。 在正常操作状态下，处理器不涉及存储器事务。 在接收到访问存储器位置的事务指令时，处理器转换到事务操作状态。 在事务操作状态下，处理器执行对高速缓存行的更改和与存储器位置相关联的数据。 在事务操作状态下，数据和高速缓存行的任何更改对于计算系统中的其他处理器是不可见的。 响应于接收到提交指令，处理器进入提交操作状态时，这些更改变得可见。 更改变为可见后，处理器返回到正常运行状态。 如果在接收提交指令之前发生中止事件，则处理器转换到中止操作状态，其中对数据和高速缓存行的任何改变被丢弃。