公开(公告)号：US11035900B2

公开(公告)日：2021-06-15

申请号：US16240697

申请日：2019-01-04

Applicant: CREDO TECHNOLOGY GROUP LIMITED

Inventor： Arshan Aga ,  Nianwei Xing

IPC: G01R31/3177 ,  G01R31/317 ,  H03M9/00

Abstract: Scan-chain testing of a semiconductor chip may be performed entirely via a deserializer port. In one illustrative device embodiment, a semiconductor chip includes at least one deserializer having: a serial-to-parallel converter coupled to a pair of differential signal input pins; a scan-chain receiver circuit coupled to at least one of the pair of differential signal input pins in parallel with the serial-to-parallel converter to receive a scan-chain test input data stream; a scan-chain test logic circuit that loads the scan-chain test input data stream into a scan chain and extracts a scan-chain test result data stream from the scan chain; and a scan-chain transmit circuit that drives the pair of differential signal input pins with the scan-chain test result data stream. If multiple SerDes blocks exist on the chip, the deserializer ports may be employed in parallel for input and output of test data streams.

公开(公告)号：US20200041565A1

公开(公告)日：2020-02-06

申请号：US16240697

申请日：2019-01-04

Applicant: CREDO TECHNOLOGY GROUP LIMITED

Inventor： Arshan Aga ,  Nianwei Xing

IPC: G01R31/3177 ,  G01R31/317

Abstract: Scan-chain testing of a semiconductor chip may be performed entirely via a deserializer port. In one illustrative device embodiment, a semiconductor chip includes at least one deserializer having: a serial-to-parallel converter coupled to a pair of differential signal input pins; a scan-chain receiver circuit coupled to at least one of the pair of differential signal input pins in parallel with the serial-to-parallel converter to receive a scan-chain test input data stream; a scan-chain test logic circuit that loads the scan-chain test input data stream into a scan chain and extracts a scan-chain test result data stream from the scan chain; and a scan-chain transmit circuit that drives the pair of differential signal input pins with the scan-chain test result data stream. If multiple SerDes blocks exist on the chip, the deserializer ports may be employed in parallel for input and output of test data streams.