公开(公告)号：US11035900B2

公开(公告)日：2021-06-15

申请号：US16240697

申请日：2019-01-04

Applicant: CREDO TECHNOLOGY GROUP LIMITED

Inventor： Arshan Aga ,  Nianwei Xing

IPC: G01R31/3177 ,  G01R31/317 ,  H03M9/00

Abstract: Scan-chain testing of a semiconductor chip may be performed entirely via a deserializer port. In one illustrative device embodiment, a semiconductor chip includes at least one deserializer having: a serial-to-parallel converter coupled to a pair of differential signal input pins; a scan-chain receiver circuit coupled to at least one of the pair of differential signal input pins in parallel with the serial-to-parallel converter to receive a scan-chain test input data stream; a scan-chain test logic circuit that loads the scan-chain test input data stream into a scan chain and extracts a scan-chain test result data stream from the scan chain; and a scan-chain transmit circuit that drives the pair of differential signal input pins with the scan-chain test result data stream. If multiple SerDes blocks exist on the chip, the deserializer ports may be employed in parallel for input and output of test data streams.

公开(公告)号：US10778236B2

公开(公告)日：2020-09-15

申请号：US16240702

申请日：2019-01-04

Applicant: CREDO TECHNOLOGY GROUP LIMITED

Inventor： Arshan Aga ,  Xiang Gao ,  Ni Xu

IPC: H03L7/099 ,  H03L7/197 ,  H03L7/089 ,  H03K19/20

Abstract: An illustrative PLL circuit and method for generating a clock signal over a wide frequency range without gaps. In one illustrative embodiment, an extended-range PLL includes: a phase comparator that determines a phase error between a reference clock and a feedback clock; a loop filter that converts the phase error into a control signal; a voltage controlled oscillator (VCO) that provides a generated clock signal having a generated clock frequency determined by the control signal; a divide-by-1.5 block that produces a reduced-frequency clock signal in response to the generated clock signal; and a multiplexer that selects one of the generated clock signal and the reduced-frequency clock signal as a selected clock signal.

公开(公告)号：US20200041565A1

公开(公告)日：2020-02-06

申请号：US16240697

申请日：2019-01-04

Applicant: CREDO TECHNOLOGY GROUP LIMITED

Inventor： Arshan Aga ,  Nianwei Xing

IPC: G01R31/3177 ,  G01R31/317

Abstract: Scan-chain testing of a semiconductor chip may be performed entirely via a deserializer port. In one illustrative device embodiment, a semiconductor chip includes at least one deserializer having: a serial-to-parallel converter coupled to a pair of differential signal input pins; a scan-chain receiver circuit coupled to at least one of the pair of differential signal input pins in parallel with the serial-to-parallel converter to receive a scan-chain test input data stream; a scan-chain test logic circuit that loads the scan-chain test input data stream into a scan chain and extracts a scan-chain test result data stream from the scan chain; and a scan-chain transmit circuit that drives the pair of differential signal input pins with the scan-chain test result data stream. If multiple SerDes blocks exist on the chip, the deserializer ports may be employed in parallel for input and output of test data streams.

公开(公告)号：US11300613B2

公开(公告)日：2022-04-12

申请号：US17022311

申请日：2020-09-16

Applicant: Credo Technology Group Limited

Inventor： Arshan Aga ,  Haoli Qian ,  Junqing Sun ,  James Bartenslager

IPC: G01R31/317 ,  G01R29/26

Abstract: A method of assessing the ability of one or more multi-die circuit elements to tolerate the presence of jitter in intra-package. The method includes: providing a first die having a set of transmitters for digital communications, the set of transmitters comprising a first transmitter and a second transmitter; providing a second die having a set of receivers for digital communications; providing a performance monitor; coupling, using an intra-package trace, a first transmit signal from the first transmitter to a receiver of the set of receivers; coupling a second transmit signal from the second transmitter to an external pin; supplying an input signal that induces jitter in the first and second transmit signals; measuring jitter in the second transmit signal via the external pin; and determining, using the performance monitor, a performance characteristic of the second die.

公开(公告)号：US20200220550A1

公开(公告)日：2020-07-09

申请号：US16240702

申请日：2019-01-04

Applicant: CREDO TECHNOLOGY GROUP LIMITED

Inventor： Arshan Aga ,  Xiang Gao ,  Ni Xu

IPC: H03L7/197 ,  H03L7/089 ,  H03L7/099

Abstract: An illustrative PLL circuit and method for generating a clock signal over a wide frequency range without gaps. In one illustrative embodiment, an extended-range PLL includes: a phase comparator that determines a phase error between a reference clock and a feedback clock; a loop filter that converts the phase error into a control signal; a voltage controlled oscillator (VCO) that provides a generated clock signal having a generated clock frequency determined by the control signal; a divide-by-1.5 block that produces a reduced-frequency clock signal in response to the generated clock signal; and a multiplexer that selects one of the generated clock signal and the reduced-frequency clock signal as a selected clock signal.