公开(公告)号：US20070070729A1

公开(公告)日：2007-03-29

申请号：US11217503

申请日：2005-09-02

申请人： Chen-Chi Huang ,  Tsan-Lin Chen ,  Shang-Pin Huang ,  Chih-Yuan Wu

发明人： Chen-Chi Huang ,  Tsan-Lin Chen ,  Shang-Pin Huang ,  Chih-Yuan Wu

IPC分类号： G11C7/00

CPC分类号： G11C16/32

摘要： A high access rate flash control provided for accessing more than one flash memory chip having different access timing specifications is disclosed. The controller comprises a read/write (R/W) pulse generator, a R/W delay chain circuit, a sampling delay chain circuit, a bi-directional feedback pad (PAD1), a data bus sampler, and a second pad (PAD2). In an embodiment, the flash controller using a fix clock to generate synchronized Read/Write pulse which is then appropriated adjusted by the R/W delay chain circuit to provide optimum R/W control signal. The adjusted R/W signal is than outputted by a bi-directional pad to flash memory chips. With the external signal feedback function, the bi-directional pad has associated with the sampling delay chain, the time latency due to pads can be eliminated nearly. Thus, the flash controller can approach high rate to access flash chips.

摘要翻译： 公开了提供用于访问具有不同访问时序规范的多个闪存芯片的高访问速率闪存控制。 控制器包括读/写（R / W）脉冲发生器，R / W延迟链电路，采样延迟链电路，双向反馈焊盘（PAD1），数据总线采样器和第二焊盘 PAD 2）。 在一个实施例中，闪存控制器使用固定时钟来产生同步的读/写脉冲，然后由R / W延迟链电路调整该读/写脉冲以提供最佳的R / W控制信号。 调整的R / W信号不是由双向键盘输出到闪存芯片。 利用外部信号反馈功能，双向焊盘与采样延迟链相关联，由于焊盘引起的时间延迟几乎可以消除。 因此，闪存控制器可以接近高速率来访问闪存芯片。

公开(公告)号：US07230863B2

公开(公告)日：2007-06-12

申请号：US11217503

申请日：2005-09-02

申请人： Chen-Chi Huang ,  Tsan-Lin Chen ,  Shang-Pin Huang ,  Chih-Yuan Wu

发明人： Chen-Chi Huang ,  Tsan-Lin Chen ,  Shang-Pin Huang ,  Chih-Yuan Wu

IPC分类号： G11C7/00

CPC分类号： G11C16/32

摘要： A high access rate flash control provided for accessing more than one flash memory chip having different access timing specifications is disclosed. The controller comprises a read/write(R/W) pulse generator, a R/W delay chain circuit, a sampling delay chain circuit, a bi-directional feedback pad (PAD1), a data bus sampler, and a second pad (PAD 2). In an embodiment, the flash controller using a fix clock to generate synchronized Read/Write pulse which is then appropriated adjusted by the R/W delay chain circuit to provide optimum R/W control signal. The adjusted R/W signal is than outputted by a bi-directional pad to flash memory chips. With the external signal feedback function, the bi-directional pad has associated with the sampling delay chain, the time latency due to pads can be eliminated nearly. Thus, the flash controller can approach high rate to access flash chips.

摘要翻译： 公开了提供用于访问具有不同访问时序规范的多个闪存芯片的高访问速率闪存控制。 控制器包括读/写（R / W）脉冲发生器，R / W延迟链电路，采样延迟链电路，双向反馈焊盘（PAD1），数据总线采样器和第二焊盘 PAD 2）。 在一个实施例中，闪存控制器使用固定时钟来产生同步的读/写脉冲，然后由R / W延迟链电路调整该读/写脉冲以提供最佳的R / W控制信号。 调整的R / W信号不是由双向键盘输出到闪存芯片。 利用外部信号反馈功能，双向焊盘与采样延迟链相关联，由于焊盘引起的时间延迟几乎可以消除。 因此，闪存控制器可以接近高速率来访问闪存芯片。