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1.发明授权公开(公告)号：US07737381B2
公开(公告)日：2010-06-15
申请号：US11657615
申请日：2007-01-25
申请人： Hung-Ming Tai , Nang-Chian Shie , Tsan-Lin Chen
发明人： Hung-Ming Tai , Nang-Chian Shie , Tsan-Lin Chen
IPC分类号： B23H7/32
CPC分类号： G01Q70/16 , C01B32/16 , C01B2202/34 , G01Q70/12 , Y10S977/856
摘要： This invention relates to a method and apparatus for controlling the length of a carbon nanotube, in cooperation with a substrate having at least one reference level on a surface of the substrate on which at least one carbon nanotube is formed, comprising at least one positioning platform for mounting and calibrating the substrate; a discharging electrode mounted on one side of the positioning platform to cut the carbon nanotube wherein the position of the discharging electrode can be calibrated with the positioning platform; a piezoelectric actuator for calibrating the position of the discharging electrode or the height of the discharging electrode relative to the substrate reference level; a position sensor for detection of the height of the substrate; and a voltage pulse supplying means for applying a voltage pulse to the discharging electrode to cut the carbon nanotube.
摘要翻译： 本发明涉及一种用于控制碳纳米管的长度的方法和装置，与在其上形成有至少一个碳纳米管的基底的表面上具有至少一个参考水平的基底配合，包括至少一个定位平台 用于安装和校准基板; 放电电极安装在定位平台的一侧以切割碳纳米管，其中放电电极的位置可以用定位平台校准; 用于校准放电电极的位置或放电电极相对于衬底基准电平的高度的压电致动器; 用于检测基板的高度的位置传感器; 以及电压脉冲提供装置，用于向放电电极施加电压脉冲以切割碳纳米管。
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公开(公告)号：US20070119372A1
公开(公告)日：2007-05-31
申请号：US11657615
申请日：2007-01-25
申请人： Hung-Ming Tai , Nang-Chian Shie , Tsan-Lin Chen
发明人： Hung-Ming Tai , Nang-Chian Shie , Tsan-Lin Chen
CPC分类号： G01Q70/16 , C01B32/16 , C01B2202/34 , G01Q70/12 , Y10S977/856
摘要： This invention relates to a method and apparatus for controlling the length of a carbon nanotube, in cooperation with a substrate having at least one reference level on a surface of the substrate on which at least one carbon nanotube is formed, comprising at least one positioning platform for mounting and calibrating the substrate; a discharging electrode mounted on one side of the positioning platform to cut the carbon nanotube wherein the position of the discharging electrode can be calibrated with the positioning platform; a piezoelectric actuator for calibrating the position of the discharging electrode or the height of the discharging electrode relative to the substrate reference level; a position sensor for detection of the height of the substrate; and a voltage pulse supplying means for applying a voltage pulse to the discharging electrode to cut the carbon nanotube.
摘要翻译： 本发明涉及一种用于控制碳纳米管的长度的方法和装置，与在其上形成有至少一个碳纳米管的基底的表面上具有至少一个参考水平的基底配合，包括至少一个定位平台 用于安装和校准基板; 放电电极安装在定位平台的一侧以切割碳纳米管，其中放电电极的位置可以用定位平台校准; 用于校准放电电极的位置或放电电极相对于衬底基准电平的高度的压电致动器; 用于检测基板的高度的位置传感器; 以及电压脉冲提供装置，用于向放电电极施加电压脉冲以切割碳纳米管。
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公开(公告)号：US20070070729A1
公开(公告)日：2007-03-29
申请号：US11217503
申请日：2005-09-02
申请人： Chen-Chi Huang , Tsan-Lin Chen , Shang-Pin Huang , Chih-Yuan Wu
发明人： Chen-Chi Huang , Tsan-Lin Chen , Shang-Pin Huang , Chih-Yuan Wu
IPC分类号： G11C7/00
CPC分类号： G11C16/32
摘要： A high access rate flash control provided for accessing more than one flash memory chip having different access timing specifications is disclosed. The controller comprises a read/write (R/W) pulse generator, a R/W delay chain circuit, a sampling delay chain circuit, a bi-directional feedback pad (PAD1), a data bus sampler, and a second pad (PAD2). In an embodiment, the flash controller using a fix clock to generate synchronized Read/Write pulse which is then appropriated adjusted by the R/W delay chain circuit to provide optimum R/W control signal. The adjusted R/W signal is than outputted by a bi-directional pad to flash memory chips. With the external signal feedback function, the bi-directional pad has associated with the sampling delay chain, the time latency due to pads can be eliminated nearly. Thus, the flash controller can approach high rate to access flash chips.
摘要翻译： 公开了提供用于访问具有不同访问时序规范的多个闪存芯片的高访问速率闪存控制。 控制器包括读/写（R / W）脉冲发生器，R / W延迟链电路，采样延迟链电路，双向反馈焊盘（PAD1），数据总线采样器和第二焊盘 PAD 2）。 在一个实施例中，闪存控制器使用固定时钟来产生同步的读/写脉冲，然后由R / W延迟链电路调整该读/写脉冲以提供最佳的R / W控制信号。 调整的R / W信号不是由双向键盘输出到闪存芯片。 利用外部信号反馈功能，双向焊盘与采样延迟链相关联，由于焊盘引起的时间延迟几乎可以消除。 因此，闪存控制器可以接近高速率来访问闪存芯片。
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公开(公告)号：US20130124931A1
公开(公告)日：2013-05-16
申请号：US13420970
申请日：2012-03-15
申请人： Tsan Lin CHEN
发明人： Tsan Lin CHEN
IPC分类号： G11C29/00
CPC分类号： G11C16/349 , G11C29/82 , G11C2029/0409 , G11C2029/4402 , H04L43/0847
摘要： In one aspect, the present disclosure provides a storage device for accounting for transmission errors to improve a usable life span of memory blocks. In some embodiments, the storage device includes: a memory array including a plurality of memory blocks; and a memory controller in communication with the memory array via an interface, wherein the memory controller is configured to detect an error event associated with data from one of the plurality of memory blocks; determine an origin of the error event; increment an error count if the origin of the error event indicates a data error in the one of the plurality of memory blocks and not if the origin of the error event indicates a transmission error; compare the error count to a threshold value; and mark the one of the plurality of memory blocks as bad when the error count exceeds the threshold value.
摘要翻译： 一方面，本公开提供了一种用于计算传输错误以提高存储块的可用寿命的存储设备。 在一些实施例中，存储设备包括：包括多个存储器块的存储器阵列; 以及存储器控制器，其经由接口与所述存储器阵列通信，其中所述存储器控制器被配置为检测与来自所述多个存储器块中的一个的数据相关联的错误事件; 确定错误事件的起源; 如果错误事件的原点指示多个存储器块之一中的数据错误，则不增加错误计数，如果错误事件的原点指示传输错误; 将错误计数与阈值进行比较; 并且当错误计数超过阈值时，将多个存储器块之一标记为坏。
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公开(公告)号：US09543035B2
公开(公告)日：2017-01-10
申请号：US13420970
申请日：2012-03-15
申请人： Tsan Lin Chen
发明人： Tsan Lin Chen
CPC分类号： G11C16/349 , G11C29/82 , G11C2029/0409 , G11C2029/4402 , H04L43/0847
摘要： In one aspect, the present disclosure provides a storage device for accounting for transmission errors to improve a usable life span of memory blocks. In some embodiments, the storage device includes: a memory array including a plurality of memory blocks; and a memory controller in communication with the memory array via an interface, wherein the memory controller is configured to detect an error event associated with data from one of the plurality of memory blocks; determine an origin of the error event; increment an error count if the origin of the error event indicates a data error in the one of the plurality of memory blocks and not if the origin of the error event indicates a transmission error; compare the error count to a threshold value; and mark the one of the plurality of memory blocks as bad when the error count exceeds the threshold value.
摘要翻译： 一方面，本公开提供了一种用于计算传输错误以提高存储块的可用寿命的存储设备。 在一些实施例中，存储设备包括：包括多个存储器块的存储器阵列; 以及存储器控制器，其经由接口与所述存储器阵列通信，其中所述存储器控制器被配置为检测与来自所述多个存储器块中的一个的数据相关联的错误事件; 确定错误事件的起源; 如果错误事件的原点指示多个存储器块之一中的数据错误，则不增加错误计数，如果错误事件的原点指示传输错误; 将错误计数与阈值进行比较; 并且当错误计数超过阈值时，将多个存储器块之一标记为坏。
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公开(公告)号：US07396564B2
公开(公告)日：2008-07-08
申请号：US10614106
申请日：2003-07-08
申请人： Hung-Ming Tai , Nang-Chian Shie , Tsan-Lin Chen
发明人： Hung-Ming Tai , Nang-Chian Shie , Tsan-Lin Chen
CPC分类号： G01Q70/16 , C01B32/16 , C01B2202/34 , G01Q70/12 , Y10S977/856
摘要： This invention relates to a method and apparatus for controlling the length of a carbon nanotube, in cooperation with a substrate having at least one reference level on a surface of the substrate on which at least one carbon nanotube is formed, comprising at least one positioning platform for mounting and calibrating the substrate; a discharging electrode mounted on one side of the positioning platform to cut the carbon nanotube wherein the position of the discharging electrode can be calibrated with the positioning platform; a piezoelectric actuator for calibrating the position of the discharging electrode or the height of the discharging electrode relative to the substrate reference level; a position sensor for detection of the height of the substrate; and a voltage pulse supplying means for applying a voltage pulse to the discharging electrode to cut the carbon nanotube.
摘要翻译： 本发明涉及一种用于控制碳纳米管的长度的方法和装置，与在其上形成有至少一个碳纳米管的基底的表面上具有至少一个参考水平的基底配合，包括至少一个定位平台 用于安装和校准基板; 放电电极安装在定位平台的一侧以切割碳纳米管，其中放电电极的位置可以用定位平台校准; 用于校准放电电极的位置或放电电极相对于衬底基准电平的高度的压电致动器; 用于检测基板的高度的位置传感器; 以及电压脉冲提供装置，用于向放电电极施加电压脉冲以切割碳纳米管。
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公开(公告)号：US07230863B2
公开(公告)日：2007-06-12
申请号：US11217503
申请日：2005-09-02
申请人： Chen-Chi Huang , Tsan-Lin Chen , Shang-Pin Huang , Chih-Yuan Wu
发明人： Chen-Chi Huang , Tsan-Lin Chen , Shang-Pin Huang , Chih-Yuan Wu
IPC分类号： G11C7/00
CPC分类号： G11C16/32
摘要： A high access rate flash control provided for accessing more than one flash memory chip having different access timing specifications is disclosed. The controller comprises a read/write(R/W) pulse generator, a R/W delay chain circuit, a sampling delay chain circuit, a bi-directional feedback pad (PAD1), a data bus sampler, and a second pad (PAD 2). In an embodiment, the flash controller using a fix clock to generate synchronized Read/Write pulse which is then appropriated adjusted by the R/W delay chain circuit to provide optimum R/W control signal. The adjusted R/W signal is than outputted by a bi-directional pad to flash memory chips. With the external signal feedback function, the bi-directional pad has associated with the sampling delay chain, the time latency due to pads can be eliminated nearly. Thus, the flash controller can approach high rate to access flash chips.
摘要翻译： 公开了提供用于访问具有不同访问时序规范的多个闪存芯片的高访问速率闪存控制。 控制器包括读/写（R / W）脉冲发生器，R / W延迟链电路，采样延迟链电路，双向反馈焊盘（PAD1），数据总线采样器和第二焊盘 PAD 2）。 在一个实施例中，闪存控制器使用固定时钟来产生同步的读/写脉冲，然后由R / W延迟链电路调整该读/写脉冲以提供最佳的R / W控制信号。 调整的R / W信号不是由双向键盘输出到闪存芯片。 利用外部信号反馈功能，双向焊盘与采样延迟链相关联，由于焊盘引起的时间延迟几乎可以消除。 因此，闪存控制器可以接近高速率来访问闪存芯片。
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公开(公告)号：US08379457B1
公开(公告)日：2013-02-19
申请号：US13420849
申请日：2012-03-15
申请人： Tsan Lin Chen
发明人： Tsan Lin Chen
IPC分类号： G11C11/34
CPC分类号： G11C16/04 , G06F13/1689 , G11C7/1051
摘要： A flash memory controller includes a controllable delay circuit configured to receive a read strobe signal from a flash memory device and to delay the read strobe signal, a data latch, coupled to the controllable delay circuit, configured to receive the delayed read strobe signal, and to capture data from the flash memory device using the delayed read strobe signal, and a calibration circuit coupled to the controllable delay circuit, configured to instruct the controllable delay circuit to delay the read strobe signal at one of a plurality of delay settings, to receive the captured data from the data latch, to determine an accuracy of the captured data, and to determine an adjustment factor for the controllable delay circuit based on the accuracy of the data captured at the data latch.
摘要翻译： 闪速存储器控制器包括可控延迟电路，其被配置为从闪存器件接收读取选通信号并延迟读选通信号，耦合到可控延迟电路的数据锁存器，被配置为接收延迟的读选通信号，以及 使用延迟的读选通信号从快闪存储器装置捕获数据，以及耦合到可控延迟电路的校准电路，配置为指示可控延迟电路以多个延迟设置之一来延迟读选通信号，以接收 来自数据锁存器的捕获数据，以确定所捕获的数据的精度，并且基于在数据锁存器处捕获的数据的精度来确定可控延迟电路的调整因子。
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