公开(公告)号：US07134058B2

公开(公告)日：2006-11-07

申请号：US09954638

申请日：2001-09-14

Applicant: Christophe Lauga

Inventor： Christophe Lauga

IPC: G11C29/00

CPC classification number: G11C29/30

Abstract: A semiconductor integrated circuit comprises a plurality of combinational logic components, a memory and a testing arrangement for configuring the memory prior to testing the combinational logic components using one or more scan chains. The arrangement includes a bit pattern generator for generating a predetermined bit pattern for writing to the memory, a switching arrangement for selectively switching the memory input to receive data from the combinational logic components or from the data generator. The switching arrangement and data generator are arranged to input the predetermined bit pattern to the memory prior to testing the integrated circuit.

Abstract translation: 半导体集成电路包括多个组合逻辑组件，存储器和用于在使用一个或多个扫描链测试组合逻辑组件之前配置存储器的测试装置。 该装置包括用于产生用于向存储器写入的预定位模式的位模式发生器，用于选择性地切换存储器输入以从组合逻辑组件或从数据发生器接收数据的切换装置。 开关布置和数据发生器被布置成在测试集成电路之前将预定的位模式输入到存储器。

公开(公告)号：US06877119B2

公开(公告)日：2005-04-05

申请号：US09954637

申请日：2001-09-14

Applicant: Christophe Lauga

Inventor： Christophe Lauga

IPC: G01R31/3185 ,  G01R31/28

CPC classification number: G01R31/318536 ,  G01R31/318547 ,  G01R31/318572

Abstract: A semiconductor integrated circuit, including a test scan arrangement has a plurality of scan chains arranged in pairs. These scan chains have input terminals for receiving test patterns, and outputs provided to compression logic such as a distributed XOR tree multiple input shift register to provide an output which is a compressed signal derived from the output test patterns. In an alternative configuration, the first scan chain of each pair is connected to the second scan chain of each pair, and the input terminal of the second scan chain becomes the output terminal. Thereby creating a longer scan chain of the first and second scan chains together with one input terminal and one output terminal. The two loads allow for efficient scanning in the first mode, or debugging to determine the position of a fault in the second mode.

Abstract translation: 包括测试扫描装置的半导体集成电路具有成对布置的多个扫描链。 这些扫描链具有用于接收测试图案的输入端子，以及提供给诸如分布式异或树多输入移位寄存器之类的压缩逻辑的输出，以提供作为从输出测试图案导出的压缩信号的输出。 在替代配置中，每对的第一扫描链连接到每对的第二扫描链，并且第二扫描链的输入端变为输出端。 从而创建第一和第二扫描链的更长的扫描链以及一个输入端和一个输出端。 两个负载允许在第一模式下进行有效的扫描，或者调试以确定第二模式中故障的位置。