公开(公告)号：US11562952B2

公开(公告)日：2023-01-24

申请号：US17245259

申请日：2021-04-30

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Craig McAdam ,  Jonathan Taylor ,  Douglas Macfarlane ,  John Kerr ,  James Munger ,  John Pavelka ,  Steven A. Atherton

IPC: H01L23/498 ,  H01L23/00

Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.

公开(公告)号：US11887924B2

公开(公告)日：2024-01-30

申请号：US17993638

申请日：2022-11-23

Applicant: Cirrus Logic International Semiconductor Ltd.

Inventor： Craig McAdam ,  Jonathan Taylor ,  Douglas Macfarlane ,  John Kerr ,  James Munger ,  John Pavelka ,  Steven A. Atherton

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L24/13 ,  H01L2224/16227

Abstract: The present disclosure relates to a chip scale package (CSP) comprising: a first set of CSP contact balls or bumps; a second set of CSP contact balls or bumps; and a channel routing region, the channel routing region being devoid of any CSP contact balls or bumps.