公开(公告)号：US20240363546A1

公开(公告)日：2024-10-31

申请号：US18769482

申请日：2024-07-11

申请人： Murata Manufacturing Co., Ltd.

发明人： Michiharu YOKOYAMA ,  Takaya NEMOTO ,  Hideki UEDA

IPC分类号： H01L23/552 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/10 ,  H01Q1/22

CPC分类号： H01L23/552 ,  H01L23/3135 ,  H01L23/538 ,  H01L24/16 ,  H01L25/105 ,  H01Q1/2283 ,  H01L2224/16227

摘要： Electronic components are included in each one of submodules. Each electronic component includes inner terminals. A first support member covers and supports, the electronic components so as to expose the inner terminals. A second support member supports the submodules. Each one of the submodules includes outer terminals, and the outer terminals are coupled to respective inner terminals and exposed from the second support member. At least one of the submodules has a first conductive film formed on at least part of the first support member.

公开(公告)号：US20240363506A1

公开(公告)日：2024-10-31

申请号：US18594792

申请日：2024-03-04

申请人： Amkor Technology Singapore Holding Pte Ltd.

发明人： Won Bae Bang ,  Kwang Seok Oh

IPC分类号： H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/14 ,  H01L23/31

CPC分类号： H01L23/49805 ,  H01L21/561 ,  H01L23/49827 ,  H01L23/49861 ,  H01L23/145 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/562 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/97 ,  H01L2924/15311

摘要： A thin semiconductor device with enhanced edge protection, and a method of manufacturing thereof. For example and without limitation, various aspects of this disclosure provide a thin semiconductor device comprising a substrate with an edge-protection region, and a method of manufacturing thereof.

公开(公告)号：US20240363463A1

公开(公告)日：2024-10-31

申请号：US18766996

申请日：2024-07-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Kuo-Chung Yee ,  Hao-Yi Tsai ,  Tin-Hao Kuo

IPC分类号： H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065

CPC分类号： H01L23/3114 ,  H01L21/486 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L21/561 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49816 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/214 ,  H01L2224/24137 ,  H01L2224/24147 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/9222 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/18162 ,  H01L2924/19041

摘要： A method includes forming a through-via from a first conductive pad of a first device die. The first conductive pad is at a top surface of the first device die. A second device die is adhered to the top surface of the first device die. The second device die has a surface conductive feature. The second device die and the through-via are encapsulated in an encapsulating material. The encapsulating material is planarized to reveal the through-via and the surface conductive feature. Redistribution lines are formed over and electrically coupled to the through-via and the surface conductive feature.

公开(公告)号：US20240363385A1

公开(公告)日：2024-10-31

申请号：US18736423

申请日：2024-06-06

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar

IPC分类号： H01L21/683 ,  G11C8/16 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L23/525 ,  H01L25/00 ,  H01L25/065 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/118 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H10B10/00 ,  H10B12/00 ,  H10B20/00 ,  H10B20/20 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40

CPC分类号： H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H10B10/00 ,  H10B10/125 ,  H10B12/053 ,  H10B12/09 ,  H10B12/20 ,  H10B12/50 ,  H10B20/00 ,  H10B41/20 ,  H10B41/40 ,  H10B41/41 ,  H10B43/20 ,  H10B43/40 ,  H01L23/3677 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81005 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H10B12/05 ,  H10B20/20

摘要： A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors, first memory cells including at least one second transistor, and overlaying the second metal layer, a third level including third transistors and overlaying the second level, a fourth level including fourth transistors, second memory cells including at least one fourth transistor, and overlaying the third level, where the first level includes memory control circuits which control writing to the second memory cells, and at least one Phase-Lock-Loop (“PLL”) circuit or at least one Digital-Lock-Loop (“DLL”) circuit.

公开(公告)号：US12132009B2

公开(公告)日：2024-10-29

申请号：US18143932

申请日：2023-05-05

申请人： Samsung Electronics Co., Ltd.

发明人： Su Chang Lee

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/16 ,  H01L23/28 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L23/29

CPC分类号： H01L23/562 ,  H01L23/16 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/0655 ,  H01L25/18 ,  H01L23/295 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/3511

摘要： A semiconductor package includes a substrate having a first surface and a second surface opposing the first surface; a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads; a semiconductor chip disposed on the first surface of the substrate and connected to the plurality of first pads; a dummy chip having a side surface facing one side surface of the semiconductor chip, disposed on the first surface of the substrate spaced apart from the semiconductor chip in a direction parallel to the first surface of the substrate, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate; an underfill disposed between the semiconductor chip and the first surface of the substrate, and having an extension portion extended along the facing side surfaces of the semiconductor chip and the dummy chip in the direction perpendicular to the first surface of the substrate, an upper end of the extension portion being disposed to be lower than the upper surface of the semiconductor chip; and a sealing material disposed on the first surface of the substrate, and sealing the semiconductor chip and the dummy chip.

公开(公告)号：US20240355796A1

公开(公告)日：2024-10-24

申请号：US18761580

申请日：2024-07-02

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： DAEHO LEE ,  JINHYUN KIM ,  WANSOO PARK

IPC分类号： H01L25/10 ,  H01L23/00 ,  H01L23/498

CPC分类号： H01L25/105 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023

摘要： A semiconductor package includes a first redistribution substrate, a first semiconductor chip disposed on the first redistribution substrate, a first mold layer that covers the first semiconductor chip and the first redistribution substrate, a second redistribution substrate disposed on the first mold layer, a second semiconductor chip disposed on the second redistribution substrate, where the second semiconductor chip includes a second-chip first conductive bump that does not overlap the first semiconductor chip, a first sidewall that overlaps the first semiconductor chip, and a second sidewall that does not overlap the first semiconductor chip, wherein the first sidewall and the second sidewall are opposite to each other, and a first mold via that penetrates the first mold layer connects the second-chip first conductive bump to the first redistribution substrate, and overlaps the second-chip first conductive bump.

公开(公告)号：US20240355762A1

公开(公告)日：2024-10-24

申请号：US18760817

申请日：2024-07-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Jiun Yi Wu ,  Chen-Hua Yu

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L23/538

CPC分类号： H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121

摘要： A device includes a redistribution structure, including conductive features; dielectric layers; and an internal support within a first dielectric layer of the dielectric layers, wherein the internal support is free of passive and active devices; a first interconnect structure attached to a first side of the redistribution structure; a second interconnect structure attached to the first side of the redistribution structure, wherein the second interconnect structure is laterally adjacent the first interconnect structure, wherein the internal support laterally overlaps both the first interconnect structure and the second interconnect structure.

公开(公告)号：US20240355752A1

公开(公告)日：2024-10-24

申请号：US18138440

申请日：2023-04-24

申请人： Intel Corporation

发明人： Telesphor KAMGAING

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/15

CPC分类号： H01L23/5386 ,  H01L21/486 ,  H01L23/15 ,  H01L23/5384 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/16 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/92125

摘要： Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a core with a first surface and a second surface, where the core comprises a glass layer. In an embodiment, a first routing layer is over the first surface of the core, where the first routing layer comprises traces with a first width. In an embodiment, a second routing layer is over the second surface of the core, where the second routing layer comprises traces with a second width that is smaller than the first width.

公开(公告)号：US20240355722A1

公开(公告)日：2024-10-24

申请号：US18761561

申请日：2024-07-02

申请人： BroadPak Corporation

发明人： Farhang YAZDANI

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L21/52 ,  H01L23/00 ,  H01L23/04 ,  H01L23/31 ,  H01L23/473 ,  H01L23/66 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

CPC分类号： H01L23/49827 ,  H01L21/486 ,  H01L21/52 ,  H01L23/04 ,  H01L23/3107 ,  H01L23/473 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/573 ,  H01L23/66 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L24/80 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2224/80203 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/207 ,  H01L2924/30107 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53183

摘要： Methods of forming secured substrates are presented. These methods involve creating signal-blocking vias and a series of meshes on various layers of an electronic substrate to mask signal traces and prevent tampering. By strategically positioning ground and power meshes on different layers, and optionally including dummy meshes, the method significantly increases the privacy and security of the electronic substrate. These techniques can also be applied inside or on integrated circuits to enhance security.

公开(公告)号：US20240355696A1

公开(公告)日：2024-10-24

申请号：US18137973

申请日：2023-04-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Hang CHANG ,  Kuang-Wei CHENG ,  Ku-Feng YANG

IPC分类号： H01L23/31 ,  H01L21/48 ,  H01L21/54 ,  H01L23/00 ,  H01L23/29 ,  H01L23/538

CPC分类号： H01L23/3192 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/54 ,  H01L23/291 ,  H01L23/3185 ,  H01L23/5384 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/05442 ,  H01L2924/186 ,  H01L2924/3511 ,  H01L2924/3512

摘要： A method of forming an IC structure includes bonding a first die to a first side of a substrate and bonding a second die to the first side of the substrate. The second die is adjacent to the first die and a gap is defined between the first and second dies. The method includes forming a first dielectric layer (DL) over the first and second dies and in the gap, forming a first opening in the first DL in the gap, forming a second DL over the first DL and in the first opening. The first DL includes a higher film stress in absolute value than the second DL.