公开(公告)号：US11218336B2

公开(公告)日：2022-01-04

申请号：US16842422

申请日：2020-04-07

Applicant: Cisco Technology, Inc.

Inventor： Swami Narayanan ,  Ambrish Mehta ,  Venkatesh Srinivasan ,  Raghava Sivaramu ,  Ayan Banerjee

IPC: H04L12/46 ,  H04L12/04 ,  H04L29/06

Abstract: Aspects of the disclosed technology address limitations relating to packet replication for multi-destination traffic, by providing methods for performing hardware-based replication in network infrastructure devices, such as switches. In some aspects, application specific integrated circuits (ASICs) resident in physical devices can be used to perform packet replication. Depending on implementation, a hardware-based replication process can include steps for receiving a first packet that includes a first outer header containing first address information, receiving a second packet including a second outer header containing a hardware replication flag, forwarding the first packet to all virtual tunnel endpoints (VTEPs) connected with the TOR switch, and performing hardware replication for the second packet based on the hardware replication flag to generate one or more unicast packets. Systems and machine readable media are also provided.

公开(公告)号：US09992111B2

公开(公告)日：2018-06-05

申请号：US15003217

申请日：2016-01-21

Applicant: Cisco Technology, Inc.

Inventor： Ayan Banerjee ,  Raghava Sivaramu ,  Ambrish Mehta ,  Swaminathan Narayanan ,  Shiv Saini ,  Mehak Mahajan

IPC: H04L1/00 ,  H04L12/749 ,  H04L12/745 ,  H04L12/933 ,  H04L12/931 ,  H04L12/741 ,  H04L12/947 ,  H04L29/12

CPC classification number: H04L45/741 ,  H04L45/74 ,  H04L45/748 ,  H04L49/10 ,  H04L49/25 ,  H04L49/352 ,  H04L61/6068

Abstract: In one embodiment an approach is provided to efficiently program routes on line cards and fabric modules in a modular router to avoid hot spots and thus avoid undesirable packet loss. Each fabric module includes two separate processors or application specific integrated circuits (ASICs). In another embodiment, each fabric module processor is replaced by a pair of fabric module processors arranged in series with each other, and each processor is responsible for routing only, e.g., IPv4 or IPv6 traffic. The pair of fabric module processors communicates with one another via a trunk line and any packet received at either one of the pair is passed to the other of the pair before being passed back to a line card.

公开(公告)号：US20190097839A1

公开(公告)日：2019-03-28

申请号：US15714761

申请日：2017-09-25

Applicant: Cisco Technology, Inc.

Inventor： Swami Narayanan ,  Ambrish Mehta ,  Venkatesh Srinivasan ,  Raghava Sivaramu ,  Ayan Banerjee

IPC: H04L12/46 ,  H04L29/06 ,  H04L12/04

Abstract: Aspects of the disclosed technology address limitations relating to packet replication for multi-destination traffic, by providing methods for performing hardware-based replication in network infrastructure devices, such as switches. In some aspects, application specific integrated circuits (ASICs) resident in physical devices can be used to perform packet replication. Depending on implementation, a hardware-based replication process can include steps for receiving a first packet that includes a first outer header containing first address information, receiving a second packet including a second outer header containing a hardware replication flag, forwarding the first packet to all virtual tunnel endpoints (VTEPs) connected with the TOR switch, and performing hardware replication for the second packet based on the hardware replication flag to generate one or more unicast packets. Systems and machine readable media are also provided.

公开(公告)号：US20200235959A1

公开(公告)日：2020-07-23

申请号：US16842422

申请日：2020-04-07

Applicant: Cisco Technology, Inc.

Inventor： Swami Narayanan ,  Ambrish Mehta ,  Venkatesh Srinivasan ,  Raghava Sivaramu ,  Ayan Banerjee

IPC: H04L12/46 ,  H04L12/04 ,  H04L29/06

Abstract: Aspects of the disclosed technology address limitations relating to packet replication for multi-destination traffic, by providing methods for performing hardware-based replication in network infrastructure devices, such as switches. In some aspects, application specific integrated circuits (ASICs) resident in physical devices can be used to perform packet replication. Depending on implementation, a hardware-based replication process can include steps for receiving a first packet that includes a first outer header containing first address information, receiving a second packet including a second outer header containing a hardware replication flag, forwarding the first packet to all virtual tunnel endpoints (VTEPs) connected with the TOR switch, and performing hardware replication for the second packet based on the hardware replication flag to generate one or more unicast packets. Systems and machine readable media are also provided.

公开(公告)号：US20170214618A1

公开(公告)日：2017-07-27

申请号：US15003217

申请日：2016-01-21

Applicant: Cisco Technology, Inc.

Inventor： Ayan Banerjee ,  Raghava Sivaramu ,  Ambrish Mehta ,  Swaminathan Narayanan ,  Shiv Saini ,  Mehak Mahajan

IPC: H04L12/64 ,  H04L12/931 ,  H04L12/933 ,  H04L12/745

CPC classification number: H04L45/741 ,  H04L45/74 ,  H04L45/748 ,  H04L49/10 ,  H04L49/25 ,  H04L49/352 ,  H04L61/6068

Abstract: In one embodiment an approach is provided to efficiently program routes on line cards and fabric modules in a modular router to avoid hot spots and thus avoid undesirable packet loss. Each fabric module includes two separate processors or application specific integrated circuits (ASICs). In another embodiment, each fabric module processor is replaced by a pair of fabric module processors arranged in series with each other, and each processor is responsible for routing only, e.g., IPv4 or IPv6 traffic. The pair of fabric module processors communicates with one another via a trunk line and any packet received at either one of the pair is passed to the other of the pair before being passed back to a line card.