利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

561 条记录 (耗时 0.02 秒)

    Attachment unit interfaces for non-identical data rate links
    1.
    发明授权
    Attachment unit interfaces for non-identical data rate links 有权

    公开(公告)号：US09742701B2

    公开(公告)日：2017-08-22

    申请号：US14462498

    申请日：2014-08-18

    申请人： BROADCOM CORPORATION

    发明人： William Calvin Woodruff ,  Alan Kwentus ,  Chao Lin ,  Richard Dale Tidstrom

    IPC分类号： H04L12/28 ,  H04L12/935 ,  H04L12/931

    CPC分类号： H04L49/30 ,  H04L49/352 ,  H04L49/356

    摘要： An apparatus for operating a low data-rate (LDR) link and legacy switch at a high data-rate (HDR) includes a first block and a second block. The first block receives input signals from the legacy switch and generates identical output signals. The second block receives the identical output signals and generates an HDR signal for communication over the LDR link coupled to an access point. Further, a media access control (MAC) interface communicates data at a first data rate with an Ethernet PHY block including a first-in-first-out (FIFO) module and a buffer. The FIFO receives data from the MAC interface at the first data rate and transmits data at a second data rate. The buffer receives data from the Ethernet port at the second data rate and transmits the received data at the first data rate in response to detection of an end of packet.

    Multi-host Ethernet controller
    3.
    发明授权
    Multi-host Ethernet controller 有权
    多主机以太网控制器

    公开(公告)号：US09590920B2

    公开(公告)日：2017-03-07

    申请号：US14112410

    申请日：2012-04-17

    申请人： Balaji Kanigicherla ,  Krishna Mohan Tandaboina ,  Laxmi Narayana Yakkala ,  Sitaram Banda ,  Chaitanya K ,  Hari Prasad Koluguri ,  Ravikanth Aluru

    发明人： Balaji Kanigicherla ,  Krishna Mohan Tandaboina ,  Laxmi Narayana Yakkala ,  Sitaram Banda ,  Chaitanya K ,  Hari Prasad Koluguri ,  Ravikanth Aluru

    IPC分类号： H04L12/931 ,  H04L12/54 ,  H04L12/40 ,  H04L12/861 ,  H04L29/06

    CPC分类号： H04L49/352 ,  H04L12/40013 ,  H04L47/50 ,  H04L49/9063 ,  H04L63/0428 ,  H04L69/16

    摘要： Described herein is a system having a multi-host Ethernet controller (102) configured to provide communication and control between two or more independent host processors (104) and a network device. In one implementation, the multi host Ethernet controller (102), having an integrated L2 switch (110) to enable a plurality of independent host systems to access same physical gigabit network port concurrently. Each host processor (104) sees the controller as PCI based independent network controller and accesses the controller using its own mini-port driver. The common programming parameters such as Link Speed or Inter Packet Gap (IPG) are programmed by a virtualization engine. Packets from network (LAN) are switched based on MAC destination address and sent to corresponding host based on MAC destination address. Packets from each host processor (104) are forwarded to network interface or other host processor (104) based on MAC destination address.

    摘要翻译： 这里描述的是具有多主机以太网控制器（102）的系统，其被配置为提供两个或多个独立主机处理器（104）和网络设备之间的通信和控制。 在一个实现中，具有集成L2交换机（110）的多主机以太网控制器（102），以使得多个独立主机系统能够同时访问相同的物理千兆网络端口。 每个主机处理器（104）将控制器视为基于PCI的独立网络控制器，并使用其自己的小型端口驱动器访问控制器。 诸如链路速度或间隔间隔（IPG）的通用编程参数由虚拟化引擎编程。 来自网络（LAN）的报文根据MAC目的地址进行切换，并根据MAC目的地址发送给相应的主机。 来自每个主处理器（104）的分组基于MAC目的地地址转发到网络接口或其他主机处理器（104）。

    Method and apparatus for aggregating input data streams
    5.
    发明授权
    Method and apparatus for aggregating input data streams 有权

    公开(公告)号：US09338100B2

    公开(公告)日：2016-05-10

    申请号：US13925564

    申请日：2013-06-24

    申请人： Foundry Networks, LLC

    发明人： Yuen Fai Wong ,  Yu-Mei Lin ,  Richard A. Grenier

    IPC分类号： H04L12/851 ,  H04L12/935 ,  H04L12/931 ,  H04L12/865

    CPC分类号： H04L47/2433 ,  H04L47/6275 ,  H04L49/30 ,  H04L49/352

    摘要： A method and apparatus aggregate a plurality of input data streams from first processors into one data stream for a second processor, the circuit and the first and second processors being provided on an electronic circuit substrate. The aggregation circuit includes (a) a plurality of ingress data ports, each ingress data port adapted to receive an input data stream from a corresponding first processor, each input data stream formed of ingress data packets, each ingress data packet including priority factors coded therein, (b) an aggregation module coupled to the ingress data ports, adapted to analyze and combine the plurality of input data steams into one aggregated data stream in response to the priority factors, (c) a memory coupled to the aggregation module, adapted to store analyzed data packets, and (d) an output data port coupled to the aggregation module, adapted to output the aggregated data stream to the second processor.

    Method and system for using lane alignment markers
    6.
    发明授权
    Method and system for using lane alignment markers 有权
    使用车道对准标记的方法和系统

    公开(公告)号：US09172661B1

    公开(公告)日：2015-10-27

    申请号：US13678406

    申请日：2012-11-15

    申请人： QLOGIC, Corporation

    发明人： Frank R. Dropps ,  Ernest G. Kohlwey ,  Leo J. Slechta, Jr.

    IPC分类号： H04L12/28 ,  H04J3/06 ,  H04L12/931

    CPC分类号： H04L49/352

    摘要： Method, system and network device for programming lane alignment markers are provided. The method includes configuring the first port having a plurality of sub-ports, as at least a dual lane port where each lane of the dual lane port is configured to receive and transmit frames; negotiating with the first network device to determine a lane alignment marker that is acceptable by the first network device; and programming the first port to identify the lane alignment marker associated with the vendor of the first network device for processing frames received from the first network device and transmitted to the first network device.

    摘要翻译： 提供了编程车道对准标记的方法，系统和网络设备。 该方法包括将具有多个子端口的第一端口配置为至少双通道端口，其中双通道端口的每个通道被配置为接收和发送帧; 与所述第一网络设备协商以确定所述第一网络设备可接受的车道对准标记; 以及编程所述第一端口以识别与所述第一网络设备的供应商相关联的所述车道对准标记，用于处理从所述第一网络设备接收并发送到所述第一网络设备的帧。

    System and method for 10/40 gigabit ethernet multi-lane gearbox
    7.
    发明授权
    System and method for 10/40 gigabit ethernet multi-lane gearbox 有权
    10/40千兆以太网多通道变速箱的系统和方法

    公开(公告)号：US09008105B2

    公开(公告)日：2015-04-14

    申请号：US13853356

    申请日：2013-03-29

    申请人： Broadcom Corporation

    发明人： Ali Ghiasi

    IPC分类号： H04L12/28 ,  H04L12/773

    CPC分类号： H04L45/60 ,  H04L49/352

    摘要： A system and method for 10/40 gigabit Ethernet multi-lane gearbox. In one embodiment, a gearbox device includes one or more inputs on a line side of the device, the one or more inputs being configured to receive four asynchronous 10 Gbit/s Ethernet channels, a marking module that is configured to insert virtual lane markers into four data flows at defined intervals to produce four marked data flows, and a 4:n physical media attachment (PMA) module that is configured to generate one or more higher-rate data flows based on the four marked data flows.

    摘要翻译： 一种用于10/40千兆以太网多通道变速箱的系统和方法。 在一个实施例中，齿轮箱装置包括在装置的线路侧上的一个或多个输入，所述一个或多个输入被配置为接收四个异步10Gbit / s以太网通道，标记模块被配置为将虚拟通道标记插入 四个数据以限定的间隔流动以产生四个标记的数据流;以及4：n物理介质连接（PMA）模块，其被配置为基于四个标记的数据流来生成一个或多个更高速率的数据流。

    Data Center Switch
    8.
    发明申请
    Data Center Switch 有权
    数据中心交换机

    公开(公告)号：US20150098473A1

    公开(公告)日：2015-04-09

    申请号：US14572675

    申请日：2014-12-16

    申请人： Broadcom Corporation

    发明人： Ariel HENDEL

    IPC分类号： H04L12/933 ,  H04L12/721

    CPC分类号： H04L49/15 ,  H04L45/72 ,  H04L49/352 ,  H04L49/356 ,  H04L49/40 ,  H04L49/45

    摘要： A method of transferring data in a network is provided. Data is received at a sub-switch of a first bundled switch having a plurality of sub-switches, the sub-switch being configured to only couple to connections external to the first bundled switch. The method also includes transferring the data from the first bundled switch using a multi-lane cable coupled to a second bundled switch, a first end of the multi-lane cable coupled to a sub-switch in the first bundled switch and a second end of the multi-lane cable coupled to at least two sub-switches in the second bundled switch.

    摘要翻译： 提供了一种在网络中传送数据的方法。 在具有多个子交换机的第一捆绑交换机的子交换机处接收数据，该子交换机被配置为仅耦合到第一捆绑交换机外部的连接。 该方法还包括使用耦合到第二捆绑交换机的多通道电缆从第一捆绑交换机传送数据，多通道电缆的第一端耦合到第一捆绑开关中的子开关，第二端 所述多通道电缆耦合到所述第二绑定开关中的至少两个子开关。

    128 Gigabit Fibre Channel Physical Architecture
    9.
    发明申请
    128 Gigabit Fibre Channel Physical Architecture 有权
    128千兆光纤通道物理架构

    公开(公告)号：US20140376566A1

    公开(公告)日：2014-12-25

    申请号：US14308143

    申请日：2014-06-18

    申请人： Brocade Communications Systems, Inc.

    发明人： Anil Mehta ,  Scott Kipp

    IPC分类号： H04L12/931

    CPC分类号： H04L49/352 ,  H04B10/40 ,  H04L12/4013 ,  H04L41/0681 ,  H04L49/30 ,  H04L49/357 ,  H04L49/40 ,  H04L69/321

    摘要： The PCS and FEC layers are combined into a single layer and the number of lanes is set at four lanes. The combination allows removal of many modules as compared to a serial arrangement of a PCS layer and an FEC layer. The reduction in the number of lanes, as compared to 100 Gbps Ethernet, provides a further simplification or cost reduction by further reducing the needed gates of an ASIC to perform the functions. Changing the lanes in the FEC layer necessitates changing the alignment marker structure. In the preferred embodiment a lane zero marker is used as the first alignment marker in each lane to allow rapid sync. A second alignment marker indicating the particular lane follows the first alignment marker.

    摘要翻译： 将PCS和FEC层组合成单个层，并将车道数设置为四个车道。 与PCS层和FEC层的串行布置相比，该组合允许移除许多模块。 与100Gbps以太网相比，车道数量的减少通过进一步减少ASIC的所需门来执行功能，进一步简化或降低成本。 改变FEC层中的通道需要改变对准标记结构。 在优选实施例中，车道零标记用作每个车道中的第一对准标记，以允许快速同步。 指示特定车道的第二对准标记遵循第一对准标记。