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公开(公告)号：US20180173673A1
公开(公告)日：2018-06-21
申请号：US15838514
申请日：2017-12-12
Inventor： Alexandros Daglis , Boris Robert Grot , Babak Falsafi
IPC: G06F15/173 , G06F12/0815 , G06F12/128 , G06F9/52
CPC classification number: G06F15/17331 , G06F9/524 , G06F9/528 , G06F12/0815 , G06F12/0831 , G06F12/128 , G06F2212/1041 , G06F2212/283 , G06F2212/507
Abstract: A distributed memory system including a plurality of chips, a plurality of nodes that are distributed across the plurality of chips such that each node is comprised within a chip, each node includes a dedicated local memory and a processor core, and each local memory is configured to be accessible over network communication, a network interface for each node, the network interface configured such that a corresponding network interface of each node is integrated in a coherence domain of the chip of the corresponding node, wherein each of the network interfaces are configured to support a one-sided operation, the network interface directly reading or writing in the dedicated local memory of the corresponding node without involving a processor core, and wherein the one-sided operation is configured such that the processor core of a corresponding node uses a protocol to directly inject a remote memory access for read or write request to the network interface of the node, the remote memory access request allowing to read or write an arbitrarily long region of a memory of a remote node,
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公开(公告)号：US10929174B2
公开(公告)日：2021-02-23
申请号：US15838514
申请日：2017-12-12
Inventor： Alexandros Daglis , Boris Robert Grot , Babak Falsafi
IPC: G06F9/46 , G06F15/173 , G06F12/0815 , G06F12/128 , G06F9/52 , G06F12/0831 , G06F12/1081
Abstract: A distributed memory system including a plurality of chips, a plurality of nodes that are distributed across the plurality of chips such that each node is comprised within a chip, each node includes a dedicated local memory and a processor core, and each local memory is configured to be accessible over network communication, a network interface for each node, the network interface configured such that a corresponding network interface of each node is integrated in a coherence domain of the chip of the corresponding node, wherein each of the network interfaces are configured to support a one-sided operation, the network interface directly reading or writing in the dedicated local memory of the corresponding node without involving a processor core, and the one-sided operation is configured such that the processor core of a corresponding node uses a protocol to directly inject a remote memory access for read or write request to the network interface of the node, the remote memory access request allowing to read or write an arbitrarily long region of a memory of a remote node.
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