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    Speculation-restricted memory region type
    1.
    发明授权
    Speculation-restricted memory region type 有权

    公开(公告)号：US11809316B2

    公开(公告)日：2023-11-07

    申请号：US17052701

    申请日：2019-05-09

    申请人： Arm Limited

    发明人： Richard William Earnshaw

    IPC分类号： G06F12/0802 ,  G06F12/14

    CPC分类号： G06F12/0802 ,  G06F12/145 ,  G06F2212/507 ,  G06F2212/60

    摘要： An apparatus has processing circuitry (18), and memory access circuitry (35) to control access to a memory system based on memory attribute data identifying each memory region as one of a plurality of region types. A speculation-restricted region type is supported, for which: at least when a first read request is non-speculatively issued to a region of the speculation-restricted type, a subsequent read request is permitted to be serviced using data obtained in response to the first read request; and for a speculatively issued read request to the region of the speculation-restricted type, at least when caching the read data would require allocation of a new entry in the cache, at least one response action, which is permitted for non-speculatively issued read requests specifying a target memory region of the speculation-restricted region type, may be prohibited from being performed before the first read request has been resolved as correct.

    COHERENCE PROTOCOL PROVIDING SPECULATIVE COHERENCE RESPONSE TO DIRECTORY PROBE
    2.
    发明申请
    COHERENCE PROTOCOL PROVIDING SPECULATIVE COHERENCE RESPONSE TO DIRECTORY PROBE 审中-公开

    公开(公告)号：US20190188138A1

    公开(公告)日：2019-06-20

    申请号：US15846392

    申请日：2017-12-19

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： GUY L. GUTHRIE ,  DAVID J. KROLAK ,  MICHAEL S. SIEGEL ,  DEREK E. WILLIAMS

    IPC分类号： G06F12/0831 ,  G06F13/16

    CPC分类号： G06F12/0831 ,  G06F13/1663 ,  G06F2212/1032 ,  G06F2212/507

    摘要： A data processing system includes first and second processing nodes and response logic coupled by an interconnect fabric. A first coherence participant in the first processing node is configured to issue a memory access request specifying a target memory block, and a second coherence participant in the second processing node is configured to issue a probe request regarding a memory region tracked in a memory coherence directory. The first coherence participant is configured to, responsive to receiving the probe request after the memory access request and before receiving a systemwide coherence response for the memory access request, detect an address collision between the probe request and the memory access request and, responsive thereto, transmit a speculative coherence response. The response logic is configured to, responsive to the speculative coherence response, provide a systemwide coherence response for the probe request that prevents the probe request from succeeding.

    CACHE APPARATUS AND A METHOD OF CACHING DATA
    4.
    发明申请
    CACHE APPARATUS AND A METHOD OF CACHING DATA 审中-公开

    公开(公告)号：US20180203802A1

    公开(公告)日：2018-07-19

    申请号：US15864062

    申请日：2018-01-08

    申请人： ARM Limited

    发明人： Ricardo Daniel Queiros ALVES ,  Nikos NIKOLERIS ,  Shidhartha DAS ,  Andreas Lars SANDBERG

    IPC分类号： G06F12/0864 ,  G06F12/0888 ,  G06F12/0862

    CPC分类号： G06F12/0864 ,  G06F12/0862 ,  G06F12/0888 ,  G06F12/0895 ,  G06F12/0897 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/507 ,  G06F2212/602 ,  Y02D10/13

    摘要： A cache apparatus is provided comprising a data storage structure providing N cache ways that each store data as a plurality of cache blocks. The data storage structure is organised as a plurality of sets, where each set comprises a cache block from each way, and further the data storage structure comprises a first data array and a second data array, where at least the second data array is set associative. A set associative tag storage structure stores a tag value for each cache block, with that set associative tag storage structure being shared by the first and second data arrays. Control circuitry applies an access likelihood policy to determine, for each set, a subset of the cache blocks of that set to be stored within the first data array. Access circuitry is then responsive to an access request to perform a lookup operation within an identified set of the set associative tag storage structure overlapped with an access operation to access within the first data array the subset of the cache blocks for the identified set. In the event of a hit condition being detected that identifies a cache block present in the first data array, that access request is then processed using the cache block accessed within the first data array. If instead a hit condition is detected that identifies a cache block absent in the first data array, then a further access operation is performed to access the identified cache block within a selected way of the second data array. Such a cache structure provides a high performance and energy efficient mechanism for storing cached data.

    Atomic Object Reads for In-Memory Rack-Scale Computing
    5.
    发明申请
    Atomic Object Reads for In-Memory Rack-Scale Computing 审中-公开

    公开(公告)号：US20180173673A1

    公开(公告)日：2018-06-21

    申请号：US15838514

    申请日：2017-12-12

    申请人： ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)

    发明人： Alexandros Daglis ,  Boris Robert Grot ,  Babak Falsafi

    IPC分类号： G06F15/173 ,  G06F12/0815 ,  G06F12/128 ,  G06F9/52

    CPC分类号： G06F15/17331 ,  G06F9/524 ,  G06F9/528 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/128 ,  G06F2212/1041 ,  G06F2212/283 ,  G06F2212/507

    摘要： A distributed memory system including a plurality of chips, a plurality of nodes that are distributed across the plurality of chips such that each node is comprised within a chip, each node includes a dedicated local memory and a processor core, and each local memory is configured to be accessible over network communication, a network interface for each node, the network interface configured such that a corresponding network interface of each node is integrated in a coherence domain of the chip of the corresponding node, wherein each of the network interfaces are configured to support a one-sided operation, the network interface directly reading or writing in the dedicated local memory of the corresponding node without involving a processor core, and wherein the one-sided operation is configured such that the processor core of a corresponding node uses a protocol to directly inject a remote memory access for read or write request to the network interface of the node, the remote memory access request allowing to read or write an arbitrarily long region of a memory of a remote node,

    Coherence processing with pre-kill mechanism to avoid duplicated transaction identifiers
    8.
    发明授权
    Coherence processing with pre-kill mechanism to avoid duplicated transaction identifiers 有权
    一致性处理与预杀机制，以避免重复的事务标识符

    公开(公告)号：US09465740B2

    公开(公告)日：2016-10-11

    申请号：US13860885

    申请日：2013-04-11

    申请人： Apple Inc.

    发明人： Erik P. Machnicki ,  Harshavardhan Kaushikkar ,  Shinye Shiu

    IPC分类号： G06F12/00 ,  G06F12/08

    CPC分类号： G06F12/0828 ,  G06F2212/1008 ,  G06F2212/507

    摘要： An apparatus for processing coherency transactions in a computing system is disclosed. The apparatus may include a request queue circuit, a duplicate tag circuit, and a memory interface unit. The request queue circuit may be configured to generate a speculative read request dependent upon a received read transaction. The duplicate tag circuit may be configured to store copies of tag from one or more cache memories, and to generate a kill message in response to a determination that data requested in the received read transaction is stored in a cache memory. The memory interface unit may be configured to store the generated speculative read request dependent upon a stall condition. The stored speculative read request may be sent to a memory controller dependent upon the stall condition. The memory interface unit may be further configured to delete the speculative read request in response to the kill message.

    摘要翻译： 公开了一种用于处理计算系统中的一致性事务的装置。 该装置可以包括请求队列电路，复制标签电路和存储器接口单元。 请求队列电路可以被配置为根据所接收的读取事务来生成推测性读取请求。 重复标签电路可以被配置为存储来自一个或多个高速缓冲存储器的标签的副本，并且响应于所接收的读取事务中请求的数据被存储在高速缓冲存储器中的确定来生成杀死消息。 存储器接口单元可以被配置为根据失速条件来存储产生的推测性读取请求。 存储的推测性读取请求可以根据失速条件发送到存储器控制器。 存储器接口单元还可以被配置为响应于杀死消息来删除推测性读取请求。