公开(公告)号：US20150180574A1

公开(公告)日：2015-06-25

申请号：US14551826

申请日：2014-11-24

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Yong-Seok CHOI ,  Hyuk-Je KWON ,  Gyung-Ock KIM

IPC: H04B10/2575

CPC classification number: H04B10/801

Abstract: Disclosed are an apparatus and method for interfacing between a central processing unit (CPU) and a main memory unit, whereby a shared cache memory unit and the main memory unit are connected to each other using one optical signal transmission line. The apparatus for interfacing between the CPU and the main memory unit includes: a master optical connection protocol engine, converting operation control signals received from a shared cache memory unit of the CPU into serial signals; a first electrical-to-optical (E/O) converter, converting the serial signals converted by the master optical connection protocol engine into optical signals; a second E/O converter, converting the optical signals converted by the first E/O converter into serial signals; a slave optical connection protocol engine, converting the serial signals converted by the second E/O converter into operation control signals; and a memory controller having access to the main memory unit.

Abstract translation: 公开了一种用于在中央处理单元（CPU）和主存储单元之间进行接口的装置和方法，由此共享高速缓冲存储器单元和主存储器单元使用一个光信号传输线相互连接。 用于在CPU和主存储器单元之间进行接口的装置包括：主光连接协议引擎，将从CPU的共享高速缓冲存储器单元接收的操作控制信号转换为串行信号; 第一电光转换器，将由主光连接协议引擎转换的串行信号转换为光信号; 第二E / O转换器，将由第一E / O转换器转换的光信号转换为串行信号; 从属光连接协议引擎，将由第二E / O转换器转换的串行信号转换成操作控制信号; 以及具有访问主存储器单元的存储器控​​制器。